X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fpci%2Fpci.c;h=157491c52da04b4ba53371a5331fae579caeabcb;hb=5afeb4bb456de129a88f38fae1573564cd53fc41;hp=3babd948056da4a25d58a8d593b0cc36761fcfc1;hpb=1733259d25015c28c47990ec11af99b3f62f811c;p=u-boot

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 3babd94805..157491c52d 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -186,72 +186,6 @@ pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
 	return -1;
 }
 
-/*
- *
- */
-
-int __pci_hose_phys_to_bus(struct pci_controller *hose,
-				phys_addr_t phys_addr,
-				unsigned long flags,
-				unsigned long skip_mask,
-				pci_addr_t *ba)
-{
-	struct pci_region *res;
-	pci_addr_t bus_addr;
-	int i;
-
-	for (i = 0; i < hose->region_count; i++) {
-		res = &hose->regions[i];
-
-		if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
-			continue;
-
-		if (res->flags & skip_mask)
-			continue;
-
-		bus_addr = phys_addr - res->phys_start + res->bus_start;
-
-		if (bus_addr >= res->bus_start &&
-			bus_addr < res->bus_start + res->size) {
-			*ba = bus_addr;
-			return 0;
-		}
-	}
-
-	return 1;
-}
-
-pci_addr_t pci_hose_phys_to_bus (struct pci_controller *hose,
-				    phys_addr_t phys_addr,
-				    unsigned long flags)
-{
-	pci_addr_t bus_addr = 0;
-	int ret;
-
-	if (!hose) {
-		puts("pci_hose_phys_to_bus: invalid hose\n");
-		return bus_addr;
-	}
-
-	/*
-	 * if PCI_REGION_MEM is set we do a two pass search with preference
-	 * on matches that don't have PCI_REGION_SYS_MEMORY set
-	 */
-	if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) {
-		ret = __pci_hose_phys_to_bus(hose, phys_addr,
-				flags, PCI_REGION_SYS_MEMORY, &bus_addr);
-		if (!ret)
-			return bus_addr;
-	}
-
-	ret = __pci_hose_phys_to_bus(hose, phys_addr, flags, 0, &bus_addr);
-
-	if (ret)
-		puts("pci_hose_phys_to_bus: invalid physical address\n");
-
-	return bus_addr;
-}
-
 int pci_hose_config_device(struct pci_controller *hose,
 			   pci_dev_t dev,
 			   unsigned long io,
@@ -503,6 +437,10 @@ int pci_hose_scan(struct pci_controller *hose)
 	}
 #endif /* CONFIG_PCI_BOOTDELAY */
 
+#ifdef CONFIG_PCI_SCAN_SHOW
+	puts("PCI:\n");
+#endif
+
 	/*
 	 * Start scan at current_busno.
 	 * PCIe will start scan at first_busno+1.