X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fpci%2Fpci.c;h=221054593ef221abb9e05e779a9cf18f3b1b5399;hb=5b2c9a6ce3ce66796e8c375133da8340c7ab2adc;hp=950a2475c500720e978ba370cfac700e08e358b9;hpb=4608f37918e5d93d6b2b6909b325a5e6fb0a2346;p=u-boot diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 950a2475c5..221054593e 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -1,20 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH * Andreas Heppel * * (C) Copyright 2002, 2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ */ /* - * PCI routines + * Old PCI routines + * + * Do not change this file. Instead, convert your board to use CONFIG_DM_PCI + * and change pci-uclass.c. */ #include #include +#include #include #include #include @@ -100,25 +103,6 @@ PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02) PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff) PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff) -/* Get a virtual address associated with a BAR region */ -void *pci_map_bar(pci_dev_t pdev, int bar, int flags) -{ - pci_addr_t pci_bus_addr; - u32 bar_response; - - /* read BAR address */ - pci_read_config_dword(pdev, bar, &bar_response); - pci_bus_addr = (pci_addr_t)(bar_response & ~0xf); - - /* - * Pass "0" as the length argument to pci_bus_to_virt. The arg - * isn't actualy used on any platform because u-boot assumes a static - * linear mapping. In the future, this could read the BAR size - * and pass that as the size if needed. - */ - return pci_bus_to_virt(pdev, pci_bus_addr, flags, 0, MAP_NOCACHE); -} - /* * */ @@ -186,211 +170,18 @@ int pci_last_busno(void) pci_dev_t pci_find_devices(struct pci_device_id *ids, int index) { struct pci_controller * hose; - u16 vendor, device; - u8 header_type; pci_dev_t bdf; - int i, bus, found_multi = 0; + int bus; for (hose = pci_get_hose_head(); hose; hose = hose->next) { -#ifdef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE - for (bus = hose->last_busno; bus >= hose->first_busno; bus--) -#else - for (bus = hose->first_busno; bus <= hose->last_busno; bus++) -#endif - for (bdf = PCI_BDF(bus, 0, 0); - bdf < PCI_BDF(bus + 1, 0, 0); - bdf += PCI_BDF(0, 0, 1)) { - if (pci_skip_dev(hose, bdf)) - continue; - - if (!PCI_FUNC(bdf)) { - pci_read_config_byte(bdf, - PCI_HEADER_TYPE, - &header_type); - - found_multi = header_type & 0x80; - } else { - if (!found_multi) - continue; - } - - pci_read_config_word(bdf, - PCI_VENDOR_ID, - &vendor); - pci_read_config_word(bdf, - PCI_DEVICE_ID, - &device); - - for (i = 0; ids[i].vendor != 0; i++) { - if (vendor == ids[i].vendor && - device == ids[i].device) { - if (index <= 0) - return bdf; - - index--; - } - } - } - } - - return -1; -} - -pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index) -{ - struct pci_device_id ids[2] = { {}, {0, 0} }; - - ids[0].vendor = vendor; - ids[0].device = device; - - return pci_find_devices(ids, index); -} - -/* - * - */ - -int __pci_hose_phys_to_bus(struct pci_controller *hose, - phys_addr_t phys_addr, - unsigned long flags, - unsigned long skip_mask, - pci_addr_t *ba) -{ - struct pci_region *res; - pci_addr_t bus_addr; - int i; - - for (i = 0; i < hose->region_count; i++) { - res = &hose->regions[i]; - - if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0) - continue; - - if (res->flags & skip_mask) - continue; - - bus_addr = phys_addr - res->phys_start + res->bus_start; - - if (bus_addr >= res->bus_start && - bus_addr < res->bus_start + res->size) { - *ba = bus_addr; - return 0; - } - } - - return 1; -} - -pci_addr_t pci_hose_phys_to_bus (struct pci_controller *hose, - phys_addr_t phys_addr, - unsigned long flags) -{ - pci_addr_t bus_addr = 0; - int ret; - - if (!hose) { - puts("pci_hose_phys_to_bus: invalid hose\n"); - return bus_addr; - } - - /* - * if PCI_REGION_MEM is set we do a two pass search with preference - * on matches that don't have PCI_REGION_SYS_MEMORY set - */ - if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) { - ret = __pci_hose_phys_to_bus(hose, phys_addr, - flags, PCI_REGION_SYS_MEMORY, &bus_addr); - if (!ret) - return bus_addr; - } - - ret = __pci_hose_phys_to_bus(hose, phys_addr, flags, 0, &bus_addr); - - if (ret) - puts("pci_hose_phys_to_bus: invalid physical address\n"); - - return bus_addr; -} - -int __pci_hose_bus_to_phys(struct pci_controller *hose, - pci_addr_t bus_addr, - unsigned long flags, - unsigned long skip_mask, - phys_addr_t *pa) -{ - struct pci_region *res; - int i; - - for (i = 0; i < hose->region_count; i++) { - res = &hose->regions[i]; - - if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0) - continue; - - if (res->flags & skip_mask) - continue; - - if (bus_addr >= res->bus_start && - (bus_addr - res->bus_start) < res->size) { - *pa = (bus_addr - res->bus_start + res->phys_start); - return 0; + for (bus = hose->first_busno; bus <= hose->last_busno; bus++) { + bdf = pci_hose_find_devices(hose, bus, ids, &index); + if (bdf != -1) + return bdf; } } - return 1; -} - -phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose, - pci_addr_t bus_addr, - unsigned long flags) -{ - phys_addr_t phys_addr = 0; - int ret; - - if (!hose) { - puts("pci_hose_bus_to_phys: invalid hose\n"); - return phys_addr; - } - - /* - * if PCI_REGION_MEM is set we do a two pass search with preference - * on matches that don't have PCI_REGION_SYS_MEMORY set - */ - if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) { - ret = __pci_hose_bus_to_phys(hose, bus_addr, - flags, PCI_REGION_SYS_MEMORY, &phys_addr); - if (!ret) - return phys_addr; - } - - ret = __pci_hose_bus_to_phys(hose, bus_addr, flags, 0, &phys_addr); - - if (ret) - puts("pci_hose_bus_to_phys: invalid physical address\n"); - - return phys_addr; -} - -void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum, - u32 addr_and_ctrl) -{ - int bar; - - bar = PCI_BASE_ADDRESS_0 + barnum * 4; - pci_hose_write_config_dword(hose, dev, bar, addr_and_ctrl); -} - -u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum) -{ - u32 addr; - int bar; - - bar = PCI_BASE_ADDRESS_0 + barnum * 4; - pci_hose_read_config_dword(hose, dev, bar, &addr); - if (addr & PCI_BASE_ADDRESS_SPACE_IO) - return addr & PCI_BASE_ADDRESS_IO_MASK; - else - return addr & PCI_BASE_ADDRESS_MEM_MASK; + return -1; } int pci_hose_config_device(struct pci_controller *hose, @@ -476,7 +267,8 @@ int pci_hose_config_device(struct pci_controller *hose, /* Disable interrupt line, if device says it wants to use interrupts */ pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin); if (pin != 0) { - pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 0xff); + pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, + PCI_INTERRUPT_LINE_DISABLE); } pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &old_command); @@ -533,91 +325,6 @@ void pci_cfgfunc_do_nothing(struct pci_controller *hose, */ extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev); -#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI_SCAN_SHOW) -const char * pci_class_str(u8 class) -{ - switch (class) { - case PCI_CLASS_NOT_DEFINED: - return "Build before PCI Rev2.0"; - break; - case PCI_BASE_CLASS_STORAGE: - return "Mass storage controller"; - break; - case PCI_BASE_CLASS_NETWORK: - return "Network controller"; - break; - case PCI_BASE_CLASS_DISPLAY: - return "Display controller"; - break; - case PCI_BASE_CLASS_MULTIMEDIA: - return "Multimedia device"; - break; - case PCI_BASE_CLASS_MEMORY: - return "Memory controller"; - break; - case PCI_BASE_CLASS_BRIDGE: - return "Bridge device"; - break; - case PCI_BASE_CLASS_COMMUNICATION: - return "Simple comm. controller"; - break; - case PCI_BASE_CLASS_SYSTEM: - return "Base system peripheral"; - break; - case PCI_BASE_CLASS_INPUT: - return "Input device"; - break; - case PCI_BASE_CLASS_DOCKING: - return "Docking station"; - break; - case PCI_BASE_CLASS_PROCESSOR: - return "Processor"; - break; - case PCI_BASE_CLASS_SERIAL: - return "Serial bus controller"; - break; - case PCI_BASE_CLASS_INTELLIGENT: - return "Intelligent controller"; - break; - case PCI_BASE_CLASS_SATELLITE: - return "Satellite controller"; - break; - case PCI_BASE_CLASS_CRYPT: - return "Cryptographic device"; - break; - case PCI_BASE_CLASS_SIGNAL_PROCESSING: - return "DSP"; - break; - case PCI_CLASS_OTHERS: - return "Does not fit any class"; - break; - default: - return "???"; - break; - }; -} -#endif /* CONFIG_CMD_PCI || CONFIG_PCI_SCAN_SHOW */ - -__weak int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev) -{ - /* - * Check if pci device should be skipped in configuration - */ - if (dev == PCI_BDF(hose->first_busno, 0, 0)) { -#if defined(CONFIG_PCI_CONFIG_HOST_BRIDGE) /* don't skip host bridge */ - /* - * Only skip configuration if "pciconfighost" is not set - */ - if (getenv("pciconfighost") == NULL) - return 1; -#else - return 1; -#endif - } - - return 0; -} - #ifdef CONFIG_PCI_SCAN_SHOW __weak int pci_print_dev(struct pci_controller *hose, pci_dev_t dev) { @@ -719,7 +426,7 @@ int pci_hose_scan(struct pci_controller *hose) if (!gd->pcidelay_done) { /* wait "pcidelay" ms (if defined)... */ - s = getenv("pcidelay"); + s = env_get("pcidelay"); if (s) { int val = simple_strtoul(s, NULL, 10); for (i = 0; i < val; i++) @@ -729,6 +436,10 @@ int pci_hose_scan(struct pci_controller *hose) } #endif /* CONFIG_PCI_BOOTDELAY */ +#ifdef CONFIG_PCI_SCAN_SHOW + puts("PCI:\n"); +#endif + /* * Start scan at current_busno. * PCIe will start scan at first_busno+1. @@ -746,6 +457,10 @@ void pci_init(void) { hose_head = NULL; + /* allow env to disable pci init/enum */ + if (env_get("pcidisable") != NULL) + return; + /* now call board specific pci_init()... */ pci_init_board(); } @@ -814,3 +529,56 @@ int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, int cap) } return 0; } + +/** + * pci_find_next_ext_capability - Find an extended capability + * + * Returns the address of the next matching extended capability structure + * within the device's PCI configuration space or 0 if the device does + * not support it. Some capabilities can occur several times, e.g., the + * vendor-specific capability, and this provides a way to find them all. + */ +int pci_find_next_ext_capability(struct pci_controller *hose, pci_dev_t dev, + int start, int cap) +{ + u32 header; + int ttl, pos = PCI_CFG_SPACE_SIZE; + + /* minimum 8 bytes per capability */ + ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; + + if (start) + pos = start; + + pci_hose_read_config_dword(hose, dev, pos, &header); + if (header == 0xffffffff || header == 0) + return 0; + + while (ttl-- > 0) { + if (PCI_EXT_CAP_ID(header) == cap && pos != start) + return pos; + + pos = PCI_EXT_CAP_NEXT(header); + if (pos < PCI_CFG_SPACE_SIZE) + break; + + pci_hose_read_config_dword(hose, dev, pos, &header); + if (header == 0xffffffff || header == 0) + break; + } + + return 0; +} + +/** + * pci_hose_find_ext_capability - Find an extended capability + * + * Returns the address of the requested extended capability structure + * within the device's PCI configuration space or 0 if the device does + * not support it. + */ +int pci_hose_find_ext_capability(struct pci_controller *hose, pci_dev_t dev, + int cap) +{ + return pci_find_next_ext_capability(hose, dev, 0, cap); +}