X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fpci%2Ftsi108_pci.c;h=c568bf9bc7d8aad02d3c387db55fa371219612d6;hb=89d48367edbc878f86db3008a4107331ef07f578;hp=d5f11e42f08e387a676e273966e5e4b58505580b;hpb=f743931f9b4d4e15c9bdfe726bef033ea1f1402c;p=u-boot

diff --git a/drivers/pci/tsi108_pci.c b/drivers/pci/tsi108_pci.c
index d5f11e42f0..c568bf9bc7 100644
--- a/drivers/pci/tsi108_pci.c
+++ b/drivers/pci/tsi108_pci.c
@@ -27,14 +27,13 @@
 
 #include <config.h>
 
-#ifdef CONFIG_TSI108_PCI
-
 #include <common.h>
 #include <pci.h>
 #include <asm/io.h>
 #include <tsi108.h>
-#ifdef CONFIG_OF_FLAT_TREE
-#include <ft_build.h>
+#if defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#include <fdt_support.h>
 #endif
 
 struct pci_controller local_hose;
@@ -48,32 +47,32 @@ void tsi108_clear_pci_error (void)
 	 * requests.
 	 */
 	/* Read PB Error Log Registers */
-	err_stat = *(volatile u32 *)(CFG_TSI108_CSR_BASE +
+	err_stat = *(volatile u32 *)(CONFIG_SYS_TSI108_CSR_BASE +
 				     TSI108_PB_REG_OFFSET + PB_ERRCS);
-	err_addr = *(volatile u32 *)(CFG_TSI108_CSR_BASE +
+	err_addr = *(volatile u32 *)(CONFIG_SYS_TSI108_CSR_BASE +
 				     TSI108_PB_REG_OFFSET + PB_AERR);
 	if (err_stat & PB_ERRCS_ES) {
 		/* Clear PCI/X bus errors if applicable */
-		if ((err_addr & 0xFF000000) == CFG_PCI_CFG_BASE) {
+		if ((err_addr & 0xFF000000) == CONFIG_SYS_PCI_CFG_BASE) {
 			/* Clear error flag */
-			*(u32 *) (CFG_TSI108_CSR_BASE +
+			*(u32 *) (CONFIG_SYS_TSI108_CSR_BASE +
 				  TSI108_PB_REG_OFFSET + PB_ERRCS) =
 			    PB_ERRCS_ES;
 
 			/* Clear read error reported in PB_ISR */
-			*(u32 *) (CFG_TSI108_CSR_BASE +
+			*(u32 *) (CONFIG_SYS_TSI108_CSR_BASE +
 				  TSI108_PB_REG_OFFSET + PB_ISR) =
 			    PB_ISR_PBS_RD_ERR;
 
 		/* Clear errors reported by PCI CSR (Normally Master Abort) */
-			pci_stat = *(volatile u32 *)(CFG_TSI108_CSR_BASE +
+			pci_stat = *(volatile u32 *)(CONFIG_SYS_TSI108_CSR_BASE +
 						     TSI108_PCI_REG_OFFSET +
 						     PCI_CSR);
-			*(volatile u32 *)(CFG_TSI108_CSR_BASE +
+			*(volatile u32 *)(CONFIG_SYS_TSI108_CSR_BASE +
 					  TSI108_PCI_REG_OFFSET + PCI_CSR) =
 			    pci_stat;
 
-			*(volatile u32 *)(CFG_TSI108_CSR_BASE +
+			*(volatile u32 *)(CONFIG_SYS_TSI108_CSR_BASE +
 					  TSI108_PCI_REG_OFFSET +
 					  PCI_IRP_STAT) = PCI_IRP_STAT_P_CSR;
 		}
@@ -95,7 +94,8 @@ unsigned int __get_pci_config_dword (u32 addr)
 			     ".section __ex_table,\"a\"\n"
 			     "       .align 2\n"
 			     "       .long 1b,3b\n"
-			     ".text":"=r"(retval):"r"(addr));
+			     ".section .text.__get_pci_config_dword"
+				: "=r"(retval) : "r"(addr));
 
 	return (retval);
 }
@@ -103,8 +103,8 @@ unsigned int __get_pci_config_dword (u32 addr)
 static int tsi108_read_config_dword (struct pci_controller *hose,
 				    pci_dev_t dev, int offset, u32 * value)
 {
-	dev &= (CFG_PCI_CFG_SIZE - 1);
-	dev |= (CFG_PCI_CFG_BASE | (offset & 0xfc));
+	dev &= (CONFIG_SYS_PCI_CFG_SIZE - 1);
+	dev |= (CONFIG_SYS_PCI_CFG_BASE | (offset & 0xfc));
 	*value = __get_pci_config_dword(dev);
 	if (0xFFFFFFFF == *value)
 		tsi108_clear_pci_error ();
@@ -114,8 +114,8 @@ static int tsi108_read_config_dword (struct pci_controller *hose,
 static int tsi108_write_config_dword (struct pci_controller *hose,
 				     pci_dev_t dev, int offset, u32 value)
 {
-	dev &= (CFG_PCI_CFG_SIZE - 1);
-	dev |= (CFG_PCI_CFG_BASE | (offset & 0xfc));
+	dev &= (CONFIG_SYS_PCI_CFG_SIZE - 1);
+	dev |= (CONFIG_SYS_PCI_CFG_BASE | (offset & 0xfc));
 
 	out_le32 ((volatile unsigned *)dev, value);
 
@@ -130,19 +130,19 @@ void pci_init_board (void)
 	hose->last_busno = 0xff;
 
 	pci_set_region (hose->regions + 0,
-		       CFG_PCI_MEMORY_BUS,
-		       CFG_PCI_MEMORY_PHYS,
-		       CFG_PCI_MEMORY_SIZE, PCI_REGION_MEM | PCI_REGION_MEMORY);
+		       CONFIG_SYS_PCI_MEMORY_BUS,
+		       CONFIG_SYS_PCI_MEMORY_PHYS,
+		       CONFIG_SYS_PCI_MEMORY_SIZE, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
 
 	/* PCI memory space */
 	pci_set_region (hose->regions + 1,
-		       CFG_PCI_MEM_BUS,
-		       CFG_PCI_MEM_PHYS, CFG_PCI_MEM_SIZE, PCI_REGION_MEM);
+		       CONFIG_SYS_PCI_MEM_BUS,
+		       CONFIG_SYS_PCI_MEM_PHYS, CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM);
 
 	/* PCI I/O space */
 	pci_set_region (hose->regions + 2,
-		       CFG_PCI_IO_BUS,
-		       CFG_PCI_IO_PHYS, CFG_PCI_IO_SIZE, PCI_REGION_IO);
+		       CONFIG_SYS_PCI_IO_BUS,
+		       CONFIG_SYS_PCI_IO_PHYS, CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO);
 
 	hose->region_count = 3;
 
@@ -162,20 +162,22 @@ void pci_init_board (void)
 	return;
 }
 
-#ifdef CONFIG_OF_FLAT_TREE
-void
-ft_pci_setup (void *blob, bd_t *bd)
+#if defined(CONFIG_OF_LIBFDT)
+void ft_pci_setup(void *blob, bd_t *bd)
 {
-	u32 *p;
-	int len;
-
-	p = (u32 *)ft_get_prop (blob, "/" OF_TSI "/pci@1000/bus-range", &len);
-	if (p != NULL) {
-		p[0] = local_hose.first_busno;
-		p[1] = local_hose.last_busno;
+	int nodeoffset;
+	int tmp[2];
+	const char *path;
+
+	nodeoffset = fdt_path_offset(blob, "/aliases");
+	if (nodeoffset >= 0) {
+		path = fdt_getprop(blob, nodeoffset, "pci", NULL);
+		if (path) {
+			tmp[0] = cpu_to_be32(local_hose.first_busno);
+			tmp[1] = cpu_to_be32(local_hose.last_busno);
+			do_fixup_by_path(blob, path, "bus-range",
+				&tmp, sizeof(tmp), 1);
+		}
 	}
-
 }
-#endif
-
-#endif	/* CONFIG_TSI108_PCI */
+#endif /* CONFIG_OF_LIBFDT */