X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fpci_auto.c;h=969167555ea27369008b7c5b53dc76f75bc9a46f;hb=00b574bdc8c54dbc9e03f63c24f62955d483e3ef;hp=3c958d3b95f184a4e663e40845cbd658dc4ad5de;hpb=debb7354d1ea4f694154818df5e5b523f5c1cc1d;p=u-boot

diff --git a/drivers/pci_auto.c b/drivers/pci_auto.c
index 3c958d3b95..969167555e 100644
--- a/drivers/pci_auto.c
+++ b/drivers/pci_auto.c
@@ -102,7 +102,8 @@ void pciauto_setup_device(struct pci_controller *hose,
 
 		/* Check the BAR type and set our address mask */
 		if (bar_response & PCI_BASE_ADDRESS_SPACE) {
-			bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
+			bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
+				   & 0xffff) + 1;
 			bar_res = io;
 
 			DEBUGF("PCI Autoconfig: BAR %d, I/O, size=0x%x, ", bar_nr, bar_size);
@@ -186,7 +187,7 @@ static void pciauto_prescan_setup_bridge(struct pci_controller *hose,
 	} else {
 		/* We don't support prefetchable memory for now, so disable */
 		pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
-		pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x1);
+		pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0);
 	}
 
 	if (pci_io) {