X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fpinctrl%2Fpinctrl_stm32.c;h=31285cdd5784da2f915f52a5fd2fe4c41079d067;hb=af15946aa081dbcd0bec7d507a2b2db4e6b6cda5;hp=5bee7fb12ad057b1bf303594c036793301643adc;hpb=b07d044d5bfa8c440b172eb3f8a9d537f82e21b6;p=u-boot diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c index 5bee7fb12a..31285cdd57 100644 --- a/drivers/pinctrl/pinctrl_stm32.c +++ b/drivers/pinctrl/pinctrl_stm32.c @@ -41,9 +41,10 @@ static int stm32_gpio_config(struct gpio_desc *desc, return 0; } + static int prep_gpio_dsc(struct stm32_gpio_dsc *gpio_dsc, u32 port_pin) { - gpio_dsc->port = (port_pin & 0xF000) >> 12; + gpio_dsc->port = (port_pin & 0x1F000) >> 12; gpio_dsc->pin = (port_pin & 0x0F00) >> 8; debug("%s: GPIO:port= %d, pin= %d\n", __func__, gpio_dsc->port, gpio_dsc->pin); @@ -93,41 +94,35 @@ static int prep_gpio_ctl(struct stm32_gpio_ctl *gpio_ctl, u32 gpio_fn, int node) return 0; } -static int stm32_pinctrl_set_state_simple(struct udevice *dev, - struct udevice *periph) +static int stm32_pinctrl_config(int offset) { u32 pin_mux[MAX_PINS_ONE_IP]; - struct fdtdec_phandle_args args; int rv, len; - /* Get node pinctrl-0 */ - rv = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev_of_offset(periph), - "pinctrl-0", 0, 0, 0, &args); - if (rv) - return rv; /* * check for "pinmux" property in each subnode (e.g. pins1 and pins2 for * usart1) of pin controller phandle "pinctrl-0" * */ - fdt_for_each_subnode(args.node, gd->fdt_blob, args.node) { + fdt_for_each_subnode(offset, gd->fdt_blob, offset) { struct stm32_gpio_dsc gpio_dsc; struct stm32_gpio_ctl gpio_ctl; int i; - len = fdtdec_get_int_array_count(gd->fdt_blob, args.node, + len = fdtdec_get_int_array_count(gd->fdt_blob, offset, "pinmux", pin_mux, ARRAY_SIZE(pin_mux)); - debug("%s: periph->name = %s, no of pinmux entries= %d\n", - __func__, periph->name, len); + debug("%s: no of pinmux entries= %d\n", __func__, len); if (len < 0) return -EINVAL; for (i = 0; i < len; i++) { struct gpio_desc desc; + debug("%s: pinmux = %x\n", __func__, *(pin_mux + i)); prep_gpio_dsc(&gpio_dsc, *(pin_mux + i)); - prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), args.node); + prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), offset); rv = uclass_get_device_by_seq(UCLASS_GPIO, - gpio_dsc.port, &desc.dev); + gpio_dsc.port, + &desc.dev); if (rv) return rv; desc.offset = gpio_dsc.pin; @@ -141,12 +136,61 @@ static int stm32_pinctrl_set_state_simple(struct udevice *dev, return 0; } +#if CONFIG_IS_ENABLED(PINCTRL_FULL) +static int stm32_pinctrl_set_state(struct udevice *dev, struct udevice *config) +{ + return stm32_pinctrl_config(dev_of_offset(config)); +} +#else /* PINCTRL_FULL */ +static int stm32_pinctrl_set_state_simple(struct udevice *dev, + struct udevice *periph) +{ + const void *fdt = gd->fdt_blob; + const fdt32_t *list; + uint32_t phandle; + int config_node; + int size, i, ret; + + list = fdt_getprop(fdt, dev_of_offset(periph), "pinctrl-0", &size); + if (!list) + return -EINVAL; + + debug("%s: periph->name = %s\n", __func__, periph->name); + + size /= sizeof(*list); + for (i = 0; i < size; i++) { + phandle = fdt32_to_cpu(*list++); + + config_node = fdt_node_offset_by_phandle(fdt, phandle); + if (config_node < 0) { + pr_err("prop pinctrl-0 index %d invalid phandle\n", i); + return -EINVAL; + } + + ret = stm32_pinctrl_config(config_node); + if (ret) + return ret; + } + + return 0; +} +#endif /* PINCTRL_FULL */ + static struct pinctrl_ops stm32_pinctrl_ops = { +#if CONFIG_IS_ENABLED(PINCTRL_FULL) + .set_state = stm32_pinctrl_set_state, +#else /* PINCTRL_FULL */ .set_state_simple = stm32_pinctrl_set_state_simple, +#endif /* PINCTRL_FULL */ }; static const struct udevice_id stm32_pinctrl_ids[] = { + { .compatible = "st,stm32f429-pinctrl" }, + { .compatible = "st,stm32f469-pinctrl" }, { .compatible = "st,stm32f746-pinctrl" }, + { .compatible = "st,stm32h743-pinctrl" }, + { .compatible = "st,stm32mp157-pinctrl" }, + { .compatible = "st,stm32mp157-z-pinctrl" }, { } };