X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fpower%2Ftwl4030.c;h=8866bf1b19edb4ae4731eabacf434c501435a3d2;hb=2399e40120f7a04fc24d496f486e5e406852538f;hp=e578ae634293e8843edae5954aaf4cb6dd78bfaa;hpb=6393c43c18a1aadcdcdd8551826eef15f50353d5;p=u-boot

diff --git a/drivers/power/twl4030.c b/drivers/power/twl4030.c
index e578ae6342..8866bf1b19 100644
--- a/drivers/power/twl4030.c
+++ b/drivers/power/twl4030.c
@@ -45,6 +45,66 @@ void twl4030_power_reset_init(void)
 	}
 }
 
+/*
+ * Power off
+ */
+void twl4030_power_off(void)
+{
+	u8 data;
+
+	/* PM master unlock (CFG and TST keys) */
+
+	data = 0xCE;
+	twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
+			     TWL4030_PM_MASTER_PROTECT_KEY, data);
+	data = 0xEC;
+	twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
+			     TWL4030_PM_MASTER_PROTECT_KEY, data);
+
+	/* VBAT start disable */
+
+	twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER,
+			    TWL4030_PM_MASTER_CFG_P1_TRANSITION, &data);
+	data &= ~TWL4030_PM_MASTER_CFG_TRANSITION_STARTON_VBAT;
+	twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
+			     TWL4030_PM_MASTER_CFG_P1_TRANSITION, data);
+
+	twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER,
+			    TWL4030_PM_MASTER_CFG_P2_TRANSITION, &data);
+	data &= ~TWL4030_PM_MASTER_CFG_TRANSITION_STARTON_VBAT;
+	twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
+			     TWL4030_PM_MASTER_CFG_P2_TRANSITION, data);
+
+	twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER,
+			    TWL4030_PM_MASTER_CFG_P3_TRANSITION, &data);
+	data &= ~TWL4030_PM_MASTER_CFG_TRANSITION_STARTON_VBAT;
+	twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
+			     TWL4030_PM_MASTER_CFG_P3_TRANSITION, data);
+
+	/* High jitter for PWRANA2 */
+
+	twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER,
+			    TWL4030_PM_MASTER_CFG_PWRANA2, &data);
+	data &= ~(TWL4030_PM_MASTER_CFG_PWRANA2_LOJIT0_LOWV |
+		  TWL4030_PM_MASTER_CFG_PWRANA2_LOJIT1_LOWV);
+	twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
+			     TWL4030_PM_MASTER_CFG_PWRANA2, data);
+
+	/* PM master lock */
+
+	data = 0xFF;
+	twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
+			     TWL4030_PM_MASTER_PROTECT_KEY, data);
+
+	/* Power off */
+
+	twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER,
+			    TWL4030_PM_MASTER_P1_SW_EVENTS, &data);
+	data |= TWL4030_PM_MASTER_SW_EVENTS_DEVOFF;
+	twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
+			     TWL4030_PM_MASTER_P1_SW_EVENTS, data);
+}
+
 /*
  * Set Device Group and Voltage
  */
@@ -91,17 +151,23 @@ void twl4030_power_init(void)
 				TWL4030_PM_RECEIVER_DEV_GRP_P1);
 }
 
-void twl4030_power_mmc_init(void)
+void twl4030_power_mmc_init(int dev_index)
 {
-	/* Set VMMC1 to 3.15 Volts */
-	twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VMMC1_DEDICATED,
-				TWL4030_PM_RECEIVER_VMMC1_VSEL_32,
-				TWL4030_PM_RECEIVER_VMMC1_DEV_GRP,
-				TWL4030_PM_RECEIVER_DEV_GRP_P1);
+	if (dev_index == 0) {
+		/* Set VMMC1 to 3.15 Volts */
+		twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VMMC1_DEDICATED,
+					TWL4030_PM_RECEIVER_VMMC1_VSEL_32,
+					TWL4030_PM_RECEIVER_VMMC1_DEV_GRP,
+					TWL4030_PM_RECEIVER_DEV_GRP_P1);
 
-	/* Set VMMC2 to 3.15 Volts */
-	twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VMMC2_DEDICATED,
-				TWL4030_PM_RECEIVER_VMMC2_VSEL_32,
-				TWL4030_PM_RECEIVER_VMMC2_DEV_GRP,
-				TWL4030_PM_RECEIVER_DEV_GRP_P1);
+		mdelay(100);	/* ramp-up delay from Linux code */
+	} else if (dev_index == 1) {
+		/* Set VMMC2 to 3.15 Volts */
+		twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VMMC2_DEDICATED,
+					TWL4030_PM_RECEIVER_VMMC2_VSEL_32,
+					TWL4030_PM_RECEIVER_VMMC2_DEV_GRP,
+					TWL4030_PM_RECEIVER_DEV_GRP_P1);
+
+		mdelay(100);	/* ramp-up delay from Linux code */
+	}
 }