X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fpwm%2FKconfig;h=37ea2b88eae1f8b46cac62fb3074320be719aa99;hb=d2d9bdfcf9bdd6a39119c19c644189fccbe588cc;hp=cd8f3570f06df33ca21c3fb48eed123412037427;hpb=12f229ea8f6c8e20f8fd07906eafc853c4c354a9;p=u-boot

diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index cd8f3570f0..37ea2b88ea 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -9,6 +9,15 @@ config DM_PWM
 	  frequency/period can be controlled along with the proportion of that
 	  time that the signal is high.
 
+config PWM_EXYNOS
+	bool "Enable support for the Exynos PWM"
+	depends on DM_PWM
+	help
+	  This PWM is found on Samsung Exynos 5250 and other Samsung SoCs. It
+	  supports a programmable period and duty cycle. A 32-bit counter is
+	  used. It provides 5 channels which can be independently
+	  programmed. Channel 4 (the last) is normally used as a timer.
+
 config PWM_ROCKCHIP
 	bool "Enable support for the Rockchip PWM"
 	depends on DM_PWM
@@ -17,3 +26,12 @@ config PWM_ROCKCHIP
 	  programmable period and duty cycle. A 32-bit counter is used.
 	  Various options provided in the hardware (such as capture mode and
 	  continuous/single-shot) are not supported by the driver.
+
+config PWM_TEGRA
+	bool "Enable support for the Tegra PWM"
+	depends on DM_PWM
+	help
+	  This PWM is found on Tegra 20 and other Nvidia SoCs. It supports
+	  four channels with a programmable period and duty cycle. Only a
+	  32KHz clock is supported by the driver but the duty cycle is
+	  configurable.