X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fqe%2Fqe.c;h=be09a17297c99c6f2596f3eab75bf01e2c1c9b57;hb=79e86ccb3786c8b20004db3fa10a70049456f580;hp=b5ddc4b474d0e89bde1884f6f1bd9db46d1c181d;hpb=3be2bdf5dc69b3142c1162a59bc67191c9077567;p=u-boot

diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index b5ddc4b474..be09a17297 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -11,9 +11,11 @@
 #include <command.h>
 #include "asm/errno.h"
 #include "asm/io.h"
-#include "asm/immap_qe.h"
+#include "linux/immap_qe.h"
 #include "qe.h"
 
+#define MPC85xx_DEVDISR_QE_DISABLE	0x1
+
 qe_map_t		*qe_immr = NULL;
 static qe_snum_t	snums[QE_NUM_OF_SNUM];
 
@@ -165,7 +167,7 @@ void qe_init(uint qe_base)
 	/*
 	 * Upload microcode to IRAM for those SOCs which do not have ROM in QE.
 	 */
-	qe_upload_firmware((const void *)CONFIG_SYS_QE_FMAN_FW_ADDR);
+	qe_upload_firmware((const void *)CONFIG_SYS_QE_FW_ADDR);
 
 	/* enable the microcode in IRAM */
 	out_be32(&qe_immr->iram.iready,QE_IRAM_READY);
@@ -317,7 +319,9 @@ int qe_upload_firmware(const struct qe_firmware *firmware)
 	size_t calc_size = sizeof(struct qe_firmware);
 	size_t length;
 	const struct qe_header *hdr;
-
+#ifdef CONFIG_DEEP_SLEEP
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#endif
 	if (!firmware) {
 		printf("Invalid address\n");
 		return -EINVAL;
@@ -330,6 +334,9 @@ int qe_upload_firmware(const struct qe_firmware *firmware)
 	if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
 	    (hdr->magic[2] != 'F')) {
 		printf("Not a microcode\n");
+#ifdef CONFIG_DEEP_SLEEP
+		setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_QE_DISABLE);
+#endif
 		return -EPERM;
 	}