X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fqe%2Fqe.c;h=d24651b5ba2b786e2a050cb3d98204d130365d6c;hb=aed03faa064cca56847571b13cbd4c849c6116aa;hp=345587be63ed8414d76379953a5278a04ff5a1e0;hpb=a88731a6c23113c713351847d019d23df46f26d7;p=u-boot diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index 345587be63..d24651b5ba 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -4,28 +4,20 @@ * Dave Liu * based on source code of Shlomi Gridish * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ #include "common.h" #include #include "asm/errno.h" #include "asm/io.h" -#include "asm/immap_qe.h" +#include "linux/immap_qe.h" #include "qe.h" +#ifdef CONFIG_LS102XA +#include +#endif + +#define MPC85xx_DEVDISR_QE_DISABLE 0x1 qe_map_t *qe_immr = NULL; static qe_snum_t snums[QE_NUM_OF_SNUM]; @@ -51,6 +43,7 @@ void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data) return; } +#ifdef CONFIG_QE uint qe_muram_alloc(uint size, uint align) { uint retloc; @@ -58,21 +51,22 @@ uint qe_muram_alloc(uint size, uint align) uint savebase; align_mask = align - 1; - savebase = gd->mp_alloc_base; + savebase = gd->arch.mp_alloc_base; - if ((off = (gd->mp_alloc_base & align_mask)) != 0) - gd->mp_alloc_base += (align - off); + off = gd->arch.mp_alloc_base & align_mask; + if (off != 0) + gd->arch.mp_alloc_base += (align - off); if ((off = size & align_mask) != 0) size += (align - off); - if ((gd->mp_alloc_base + size) >= gd->mp_alloc_top) { - gd->mp_alloc_base = savebase; + if ((gd->arch.mp_alloc_base + size) >= gd->arch.mp_alloc_top) { + gd->arch.mp_alloc_base = savebase; printf("%s: ran out of ram.\n", __FUNCTION__); } - retloc = gd->mp_alloc_base; - gd->mp_alloc_base += size; + retloc = gd->arch.mp_alloc_base; + gd->arch.mp_alloc_base += size; memset((void *)&qe_immr->muram[retloc], 0, size); @@ -80,6 +74,7 @@ uint qe_muram_alloc(uint size, uint align) return retloc; } +#endif void *qe_muram_addr(uint offset) { @@ -177,19 +172,30 @@ void qe_init(uint qe_base) /* * Upload microcode to IRAM for those SOCs which do not have ROM in QE. */ - qe_upload_firmware((const void *)CONFIG_SYS_QE_FMAN_FW_ADDR); + qe_upload_firmware((const void *)CONFIG_SYS_QE_FW_ADDR); /* enable the microcode in IRAM */ out_be32(&qe_immr->iram.iready,QE_IRAM_READY); #endif - gd->mp_alloc_base = QE_DATAONLY_BASE; - gd->mp_alloc_top = gd->mp_alloc_base + QE_DATAONLY_SIZE; + gd->arch.mp_alloc_base = QE_DATAONLY_BASE; + gd->arch.mp_alloc_top = gd->arch.mp_alloc_base + QE_DATAONLY_SIZE; qe_sdma_init(); qe_snums_init(); } +#ifdef CONFIG_U_QE +void u_qe_init(void) +{ + uint qe_base = CONFIG_SYS_IMMR + 0x01400000; /* QE immr base */ + qe_immr = (qe_map_t *)qe_base; + + u_qe_upload_firmware((const void *)CONFIG_SYS_QE_FW_ADDR); + out_be32(&qe_immr->iram.iready, QE_IRAM_READY); +} +#endif + void qe_reset(void) { qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID, @@ -220,8 +226,9 @@ void qe_assign_page(uint snum, uint para_ram_base) from CLKn pin, we have te change the function. */ -#define BRG_CLK (gd->brg_clk) +#define BRG_CLK (gd->arch.brg_clk) +#ifdef CONFIG_QE int qe_set_brg(uint brg, uint rate) { volatile uint *bp; @@ -249,6 +256,7 @@ int qe_set_brg(uint brg, uint rate) return 0; } +#endif /* Set ethernet MII clock master */ @@ -329,7 +337,13 @@ int qe_upload_firmware(const struct qe_firmware *firmware) size_t calc_size = sizeof(struct qe_firmware); size_t length; const struct qe_header *hdr; - +#ifdef CONFIG_DEEP_SLEEP +#ifdef CONFIG_LS102XA + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; +#else + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#endif +#endif if (!firmware) { printf("Invalid address\n"); return -EINVAL; @@ -341,7 +355,10 @@ int qe_upload_firmware(const struct qe_firmware *firmware) /* Check the magic */ if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') || (hdr->magic[2] != 'F')) { - printf("Not a microcode\n"); + printf("QE microcode not found\n"); +#ifdef CONFIG_DEEP_SLEEP + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_QE_DISABLE); +#endif return -EPERM; } @@ -434,6 +451,135 @@ int qe_upload_firmware(const struct qe_firmware *firmware) return 0; } +#ifdef CONFIG_U_QE +/* + * Upload a microcode to the I-RAM at a specific address. + * + * See docs/README.qe_firmware for information on QE microcode uploading. + * + * Currently, only version 1 is supported, so the 'version' field must be + * set to 1. + * + * The SOC model and revision are not validated, they are only displayed for + * informational purposes. + * + * 'calc_size' is the calculated size, in bytes, of the firmware structure and + * all of the microcode structures, minus the CRC. + * + * 'length' is the size that the structure says it is, including the CRC. + */ +int u_qe_upload_firmware(const struct qe_firmware *firmware) +{ + unsigned int i; + unsigned int j; + u32 crc; + size_t calc_size = sizeof(struct qe_firmware); + size_t length; + const struct qe_header *hdr; +#ifdef CONFIG_DEEP_SLEEP +#ifdef CONFIG_LS102XA + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; +#else + ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#endif +#endif + if (!firmware) { + printf("Invalid address\n"); + return -EINVAL; + } + + hdr = &firmware->header; + length = be32_to_cpu(hdr->length); + + /* Check the magic */ + if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') || + (hdr->magic[2] != 'F')) { + printf("Not a microcode\n"); +#ifdef CONFIG_DEEP_SLEEP + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_QE_DISABLE); +#endif + return -EPERM; + } + + /* Check the version */ + if (hdr->version != 1) { + printf("Unsupported version\n"); + return -EPERM; + } + + /* Validate some of the fields */ + if ((firmware->count < 1) || (firmware->count > MAX_QE_RISC)) { + printf("Invalid data\n"); + return -EINVAL; + } + + /* Validate the length and check if there's a CRC */ + calc_size += (firmware->count - 1) * sizeof(struct qe_microcode); + + for (i = 0; i < firmware->count; i++) + /* + * For situations where the second RISC uses the same microcode + * as the first, the 'code_offset' and 'count' fields will be + * zero, so it's okay to add those. + */ + calc_size += sizeof(u32) * + be32_to_cpu(firmware->microcode[i].count); + + /* Validate the length */ + if (length != calc_size + sizeof(u32)) { + printf("Invalid length\n"); + return -EPERM; + } + + /* + * Validate the CRC. We would normally call crc32_no_comp(), but that + * function isn't available unless you turn on JFFS support. + */ + crc = be32_to_cpu(*(u32 *)((void *)firmware + calc_size)); + if (crc != (crc32(-1, (const void *)firmware, calc_size) ^ -1)) { + printf("Firmware CRC is invalid\n"); + return -EIO; + } + + /* + * If the microcode calls for it, split the I-RAM. + */ + if (!firmware->split) { + out_be16(&qe_immr->cp.cercr, + in_be16(&qe_immr->cp.cercr) | QE_CP_CERCR_CIR); + } + + if (firmware->soc.model) + printf("Firmware '%s' for %u V%u.%u\n", + firmware->id, be16_to_cpu(firmware->soc.model), + firmware->soc.major, firmware->soc.minor); + else + printf("Firmware '%s'\n", firmware->id); + + /* Loop through each microcode. */ + for (i = 0; i < firmware->count; i++) { + const struct qe_microcode *ucode = &firmware->microcode[i]; + + /* Upload a microcode if it's present */ + if (ucode->code_offset) + qe_upload_microcode(firmware, ucode); + + /* Program the traps for this processor */ + for (j = 0; j < 16; j++) { + u32 trap = be32_to_cpu(ucode->traps[j]); + + if (trap) + out_be32(&qe_immr->rsp[i].tibcr[j], trap); + } + + /* Enable traps */ + out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr)); + } + + return 0; +} +#endif + struct qe_firmware_info *qe_get_firmware_info(void) { return qe_firmware_uploaded ? &qe_firmware_info : NULL;