X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fqe%2Fuec.c;h=69cdf9444a6f522042bcddd577ab5998eeca658d;hb=069b746ad9e66ab75973020f992e059c06cf3a7c;hp=3e46e3515faba49cc9c873cdc3e9ef3e1c66d50f;hpb=c829ff2e3d1bec9b2019480d82638149327db99e;p=u-boot diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index 3e46e3515f..69cdf9444a 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -1,35 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2006-2011 Freescale Semiconductor, Inc. * * Dave Liu - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA */ -#include "common.h" -#include "net.h" -#include "malloc.h" -#include "asm/errno.h" -#include "asm/io.h" -#include "asm/immap_qe.h" -#include "qe.h" +#include +#include +#include +#include +#include +#include #include "uccf.h" #include "uec.h" #include "uec_phy.h" #include "miiphy.h" +#include #include /* Default UTBIPAR SMI address */ @@ -580,8 +566,7 @@ static void phy_change(struct eth_device *dev) { uec_private_t *uec = (uec_private_t *)dev->priv; -#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \ - defined(CONFIG_P1021) || defined(CONFIG_P1025) +#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025) ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); /* QE9 and QE12 need to be set for enabling QE MII managment signals */ @@ -592,8 +577,7 @@ static void phy_change(struct eth_device *dev) /* Update the link, speed, duplex */ uec->mii_info->phyinfo->read_status(uec->mii_info); -#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \ - defined(CONFIG_P1021) || defined(CONFIG_P1025) +#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025) /* * QE12 is muxed with LBCTL, it needs to be released for enabling * LBCTL signal for LBC usage. @@ -638,20 +622,20 @@ static int uec_miiphy_find_dev_by_name(const char *devname) * Returns: * 0 on success */ -static int uec_miiphy_read(const char *devname, unsigned char addr, - unsigned char reg, unsigned short *value) +static int uec_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg) { + unsigned short value = 0; int devindex = 0; - if (devname == NULL || value == NULL) { + if (bus->name == NULL) { debug("%s: NULL pointer given\n", __FUNCTION__); } else { - devindex = uec_miiphy_find_dev_by_name(devname); + devindex = uec_miiphy_find_dev_by_name(bus->name); if (devindex >= 0) { - *value = uec_read_phy_reg(devlist[devindex], addr, reg); + value = uec_read_phy_reg(devlist[devindex], addr, reg); } } - return 0; + return value; } /* @@ -660,15 +644,15 @@ static int uec_miiphy_read(const char *devname, unsigned char addr, * Returns: * 0 on success */ -static int uec_miiphy_write(const char *devname, unsigned char addr, - unsigned char reg, unsigned short value) +static int uec_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg, + u16 value) { int devindex = 0; - if (devname == NULL) { + if (bus->name == NULL) { debug("%s: NULL pointer given\n", __FUNCTION__); } else { - devindex = uec_miiphy_find_dev_by_name(devname); + devindex = uec_miiphy_find_dev_by_name(bus->name); if (devindex >= 0) { uec_write_phy_reg(devlist[devindex], addr, reg, value); } @@ -1208,16 +1192,14 @@ static int uec_init(struct eth_device* dev, bd_t *bd) uec_private_t *uec; int err, i; struct phy_info *curphy; -#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \ - defined(CONFIG_P1021) || defined(CONFIG_P1025) +#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025) ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif uec = (uec_private_t *)dev->priv; if (uec->the_first_run == 0) { -#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \ - defined(CONFIG_P1021) || defined(CONFIG_P1025) +#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025) /* QE9 and QE12 need to be set for enabling QE MII managment signals */ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9); setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12); @@ -1249,8 +1231,7 @@ static int uec_init(struct eth_device* dev, bd_t *bd) udelay(100000); } while (1); -#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \ - defined(CONFIG_P1021) || defined(CONFIG_P1025) +#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025) /* QE12 needs to be released for enabling LBCTL signal*/ clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12); #endif @@ -1288,7 +1269,7 @@ static void uec_halt(struct eth_device* dev) uec_stop(uec, COMM_DIR_RX_AND_TX); } -static int uec_send(struct eth_device* dev, volatile void *buf, int len) +static int uec_send(struct eth_device *dev, void *buf, int len) { uec_private_t *uec; ucc_fast_private_t *uccf; @@ -1351,7 +1332,7 @@ static int uec_recv(struct eth_device* dev) if (!(status & RxBD_ERROR)) { data = BD_DATA(bd); len = BD_LENGTH(bd); - NetReceive(data, len); + net_process_received_packet(data, len); } else { printf("%s: Rx error\n", dev->name); } @@ -1417,7 +1398,17 @@ int uec_initialize(bd_t *bis, uec_info_t *uec_info) } #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - miiphy_register(dev->name, uec_miiphy_read, uec_miiphy_write); + int retval; + struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) + return -ENOMEM; + strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); + mdiodev->read = uec_miiphy_read; + mdiodev->write = uec_miiphy_write; + + retval = mdio_register(mdiodev); + if (retval < 0) + return retval; #endif return 1;