X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fqe%2Fuec_phy.h;h=7ac1ff932950cb2335cde0576a1ae91d9f069a71;hb=d1475d8aab7a6ab7ea7534a98bd20e59f150c2e3;hp=e59a940e0dd4fdc2deb6178139a7f363e513d1ed;hpb=b90296fc39a33f84bb2b0aa79bf997be495ba791;p=u-boot

diff --git a/drivers/qe/uec_phy.h b/drivers/qe/uec_phy.h
index e59a940e0d..7ac1ff9329 100644
--- a/drivers/qe/uec_phy.h
+++ b/drivers/qe/uec_phy.h
@@ -29,6 +29,11 @@
 #define MII_1000BASETCONTROL_FULLDUPLEXCAP    0x0200
 #define MII_1000BASETCONTROL_HALFDUPLEXCAP    0x0100
 
+/* 1000BT status */
+#define MII_1000BASETSTATUS	0x0a
+#define LPA_1000FULL		0x0400
+#define LPA_1000HALF		0x0200
+
 /* Cicada Extended Control Register 1 */
 #define MII_CIS8201_EXT_CON1	    0x17
 #define MII_CIS8201_EXTCON1_INIT    0x0000
@@ -72,6 +77,14 @@
 #define MII_M1011_IMASK_INIT		0x6400
 #define MII_M1011_IMASK_CLEAR		0x0000
 
+/* 88E1111 PHY Register */
+#define MII_M1111_PHY_EXT_CR            0x14
+#define MII_M1111_RX_DELAY              0x80
+#define MII_M1111_TX_DELAY              0x2
+#define MII_M1111_PHY_EXT_SR            0x1b
+#define MII_M1111_HWCFG_MODE_MASK       0xf
+#define MII_M1111_HWCFG_MODE_RGMII      0xb
+
 #define MII_DM9161_SCR			0x10
 #define MII_DM9161_SCR_INIT		0x0610
 #define MII_DM9161_SCR_RMII_INIT	0x0710