X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fram%2Fstm32_sdram.c;h=dc39f33d16a7745ccfedf571cac975bab2656b7c;hb=624d2cae3401c2e4d43c571a9b81d1f650e7703d;hp=40298112ad78fe1d26c7d02d161662a41c8b9f75;hpb=f39b90dc8c2b6da6665fa4c7dcd47d32cbe07a29;p=u-boot diff --git a/drivers/ram/stm32_sdram.c b/drivers/ram/stm32_sdram.c index 40298112ad..dc39f33d16 100644 --- a/drivers/ram/stm32_sdram.c +++ b/drivers/ram/stm32_sdram.c @@ -1,8 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ /* - * (C) Copyright 2017 - * Vikas Manocha, - * - * SPDX-License-Identifier: GPL-2.0+ + * Copyright (C) 2017, STMicroelectronics - All Rights Reserved + * Author(s): Vikas Manocha, for STMicroelectronics. */ #include @@ -11,7 +10,8 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; +#define MEM_MODE_MASK GENMASK(2, 0) +#define NOT_FOUND 0xff struct stm32_fmc_regs { /* 0x0 */ @@ -54,6 +54,12 @@ struct stm32_fmc_regs { u32 sdsr; /* SDRAM Status register */ }; +/* + * NOR/PSRAM Control register BCR1 + * FMC controller Enable, only availabe for H7 + */ +#define FMC_BCR1_FMCEN BIT(31) + /* Control register SDCR */ #define FMC_SDCR_RPIPE_SHIFT 13 /* RPIPE bit shift */ #define FMC_SDCR_RBURST_SHIFT 12 /* RBURST bit shift */ @@ -117,12 +123,29 @@ struct stm32_sdram_timing { u8 twr; u8 trcd; }; -struct stm32_sdram_params { - struct stm32_fmc_regs *base; - u8 no_sdram_banks; +enum stm32_fmc_bank { + SDRAM_BANK1, + SDRAM_BANK2, + MAX_SDRAM_BANK, +}; + +enum stm32_fmc_family { + STM32F7_FMC, + STM32H7_FMC, +}; + +struct bank_params { struct stm32_sdram_control *sdram_control; struct stm32_sdram_timing *sdram_timing; u32 sdram_ref_count; + enum stm32_fmc_bank target_bank; +}; + +struct stm32_sdram_params { + struct stm32_fmc_regs *base; + u8 no_sdram_banks; + struct bank_params bank_params[MAX_SDRAM_BANK]; + enum stm32_fmc_family family; }; #define SDRAM_MODE_BL_SHIFT 0 @@ -132,96 +155,185 @@ struct stm32_sdram_params { int stm32_sdram_init(struct udevice *dev) { struct stm32_sdram_params *params = dev_get_platdata(dev); + struct stm32_sdram_control *control; + struct stm32_sdram_timing *timing; struct stm32_fmc_regs *regs = params->base; - struct stm32_sdram_control *control = params->sdram_control; - struct stm32_sdram_timing *timing = params->sdram_timing; - - writel(control->sdclk << FMC_SDCR_SDCLK_SHIFT - | control->cas_latency << FMC_SDCR_CAS_SHIFT - | control->no_banks << FMC_SDCR_NB_SHIFT - | control->memory_width << FMC_SDCR_MWID_SHIFT - | control->no_rows << FMC_SDCR_NR_SHIFT - | control->no_columns << FMC_SDCR_NC_SHIFT - | control->rd_pipe_delay << FMC_SDCR_RPIPE_SHIFT - | control->rd_burst << FMC_SDCR_RBURST_SHIFT, - ®s->sdcr1); - - writel(timing->trcd << FMC_SDTR_TRCD_SHIFT - | timing->trp << FMC_SDTR_TRP_SHIFT - | timing->twr << FMC_SDTR_TWR_SHIFT - | timing->trc << FMC_SDTR_TRC_SHIFT - | timing->tras << FMC_SDTR_TRAS_SHIFT - | timing->txsr << FMC_SDTR_TXSR_SHIFT - | timing->tmrd << FMC_SDTR_TMRD_SHIFT, - ®s->sdtr1); - - writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_START_CLOCK, - ®s->sdcmr); - udelay(200); /* 200 us delay, page 10, "Power-Up" */ - FMC_BUSY_WAIT(regs); - - writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_PRECHARGE, - ®s->sdcmr); - udelay(100); - FMC_BUSY_WAIT(regs); - - writel((FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_AUTOREFRESH - | 7 << FMC_SDCMR_NRFS_SHIFT), ®s->sdcmr); - udelay(100); - FMC_BUSY_WAIT(regs); - - writel(FMC_SDCMR_BANK_1 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT - | control->cas_latency << SDRAM_MODE_CAS_SHIFT) - << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE, - ®s->sdcmr); - udelay(100); - FMC_BUSY_WAIT(regs); - - writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_NORMAL, - ®s->sdcmr); - FMC_BUSY_WAIT(regs); - - /* Refresh timer */ - writel((params->sdram_ref_count) << 1, ®s->sdrtr); + enum stm32_fmc_bank target_bank; + u32 ctb; /* SDCMR register: Command Target Bank */ + u32 ref_count; + u8 i; + + /* disable the FMC controller */ + if (params->family == STM32H7_FMC) + clrbits_le32(®s->bcr1, FMC_BCR1_FMCEN); + + for (i = 0; i < params->no_sdram_banks; i++) { + control = params->bank_params[i].sdram_control; + timing = params->bank_params[i].sdram_timing; + target_bank = params->bank_params[i].target_bank; + ref_count = params->bank_params[i].sdram_ref_count; + + writel(control->sdclk << FMC_SDCR_SDCLK_SHIFT + | control->cas_latency << FMC_SDCR_CAS_SHIFT + | control->no_banks << FMC_SDCR_NB_SHIFT + | control->memory_width << FMC_SDCR_MWID_SHIFT + | control->no_rows << FMC_SDCR_NR_SHIFT + | control->no_columns << FMC_SDCR_NC_SHIFT + | control->rd_pipe_delay << FMC_SDCR_RPIPE_SHIFT + | control->rd_burst << FMC_SDCR_RBURST_SHIFT, + ®s->sdcr1); + + if (target_bank == SDRAM_BANK2) + writel(control->cas_latency << FMC_SDCR_CAS_SHIFT + | control->no_banks << FMC_SDCR_NB_SHIFT + | control->memory_width << FMC_SDCR_MWID_SHIFT + | control->no_rows << FMC_SDCR_NR_SHIFT + | control->no_columns << FMC_SDCR_NC_SHIFT, + ®s->sdcr2); + + writel(timing->trcd << FMC_SDTR_TRCD_SHIFT + | timing->trp << FMC_SDTR_TRP_SHIFT + | timing->twr << FMC_SDTR_TWR_SHIFT + | timing->trc << FMC_SDTR_TRC_SHIFT + | timing->tras << FMC_SDTR_TRAS_SHIFT + | timing->txsr << FMC_SDTR_TXSR_SHIFT + | timing->tmrd << FMC_SDTR_TMRD_SHIFT, + ®s->sdtr1); + + if (target_bank == SDRAM_BANK2) + writel(timing->trcd << FMC_SDTR_TRCD_SHIFT + | timing->trp << FMC_SDTR_TRP_SHIFT + | timing->twr << FMC_SDTR_TWR_SHIFT + | timing->trc << FMC_SDTR_TRC_SHIFT + | timing->tras << FMC_SDTR_TRAS_SHIFT + | timing->txsr << FMC_SDTR_TXSR_SHIFT + | timing->tmrd << FMC_SDTR_TMRD_SHIFT, + ®s->sdtr2); + + if (target_bank == SDRAM_BANK1) + ctb = FMC_SDCMR_BANK_1; + else + ctb = FMC_SDCMR_BANK_2; + + writel(ctb | FMC_SDCMR_MODE_START_CLOCK, ®s->sdcmr); + udelay(200); /* 200 us delay, page 10, "Power-Up" */ + FMC_BUSY_WAIT(regs); + + writel(ctb | FMC_SDCMR_MODE_PRECHARGE, ®s->sdcmr); + udelay(100); + FMC_BUSY_WAIT(regs); + + writel((ctb | FMC_SDCMR_MODE_AUTOREFRESH | 7 << FMC_SDCMR_NRFS_SHIFT), + ®s->sdcmr); + udelay(100); + FMC_BUSY_WAIT(regs); + + writel(ctb | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT + | control->cas_latency << SDRAM_MODE_CAS_SHIFT) + << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE, + ®s->sdcmr); + udelay(100); + FMC_BUSY_WAIT(regs); + + writel(ctb | FMC_SDCMR_MODE_NORMAL, ®s->sdcmr); + FMC_BUSY_WAIT(regs); + + /* Refresh timer */ + writel(ref_count << 1, ®s->sdrtr); + } + + /* enable the FMC controller */ + if (params->family == STM32H7_FMC) + setbits_le32(®s->bcr1, FMC_BCR1_FMCEN); return 0; } static int stm32_fmc_ofdata_to_platdata(struct udevice *dev) { - ofnode bank_node; struct stm32_sdram_params *params = dev_get_platdata(dev); + struct bank_params *bank_params; + struct ofnode_phandle_args args; + u32 *syscfg_base; + u32 mem_remap; + ofnode bank_node; + char *bank_name; + u8 bank = 0; + int ret; - params->no_sdram_banks = dev_read_u32_default(dev, "mr-nbanks", 1); - debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks); + mem_remap = dev_read_u32_default(dev, "st,mem_remap", NOT_FOUND); + if (mem_remap != NOT_FOUND) { + ret = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0, + &args); + if (ret) { + debug("%s: can't find syscon device (%d)\n", __func__, + ret); + return ret; + } + + syscfg_base = (u32 *)ofnode_get_addr(args.node); + + /* set memory mapping selection */ + clrsetbits_le32(syscfg_base, MEM_MODE_MASK, mem_remap); + } else { + debug("%s: cannot find st,mem_remap property\n", __func__); + } dev_for_each_subnode(bank_node, dev) { - params->sdram_control = (struct stm32_sdram_control *) - ofnode_read_u8_array_ptr(bank_node, - "st,sdram-control", - sizeof(struct stm32_sdram_control)); - - if (!params->sdram_control) { - error("st,sdram-control not found for device: %s", - dev->name); + /* extract the bank index from DT */ + bank_name = (char *)ofnode_get_name(bank_node); + strsep(&bank_name, "@"); + if (!bank_name) { + pr_err("missing sdram bank index"); return -EINVAL; } - params->sdram_timing = (struct stm32_sdram_timing *) - ofnode_read_u8_array_ptr(bank_node, - "st,sdram-timing", - sizeof(struct stm32_sdram_timing)); + bank_params = ¶ms->bank_params[bank]; + strict_strtoul(bank_name, 10, + (long unsigned int *)&bank_params->target_bank); - if (!params->sdram_timing) { - error("st,sdram-timing not found for device: %s", - dev->name); + if (bank_params->target_bank >= MAX_SDRAM_BANK) { + pr_err("Found bank %d , but only bank 0 and 1 are supported", + bank_params->target_bank); return -EINVAL; } - params->sdram_ref_count = ofnode_read_u32_default(bank_node, + debug("Find bank %s %u\n", bank_name, bank_params->target_bank); + + params->bank_params[bank].sdram_control = + (struct stm32_sdram_control *) + ofnode_read_u8_array_ptr(bank_node, + "st,sdram-control", + sizeof(struct stm32_sdram_control)); + + if (!params->bank_params[bank].sdram_control) { + pr_err("st,sdram-control not found for %s", + ofnode_get_name(bank_node)); + return -EINVAL; + } + + + params->bank_params[bank].sdram_timing = + (struct stm32_sdram_timing *) + ofnode_read_u8_array_ptr(bank_node, + "st,sdram-timing", + sizeof(struct stm32_sdram_timing)); + + if (!params->bank_params[bank].sdram_timing) { + pr_err("st,sdram-timing not found for %s", + ofnode_get_name(bank_node)); + return -EINVAL; + } + + + bank_params->sdram_ref_count = ofnode_read_u32_default(bank_node, "st,sdram-refcount", 8196); + bank++; } + params->no_sdram_banks = bank; + debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks); + return 0; } @@ -236,6 +348,7 @@ static int stm32_fmc_probe(struct udevice *dev) return -EINVAL; params->base = (struct stm32_fmc_regs *)addr; + params->family = dev_get_driver_data(dev); #ifdef CONFIG_CLK struct clk clk; @@ -268,7 +381,8 @@ static struct ram_ops stm32_fmc_ops = { }; static const struct udevice_id stm32_fmc_ids[] = { - { .compatible = "st,stm32-fmc" }, + { .compatible = "st,stm32-fmc", .data = STM32F7_FMC }, + { .compatible = "st,stm32h7-fmc", .data = STM32H7_FMC }, { } };