X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fserial%2Fserial_lpuart.c;h=1212b7267634c6be6d5d948c412fe2e7d3888199;hb=914bb7ea2f9373fa59285ff77a95df73848c8f66;hp=ae471837faf56b71c0fb561e60d4e52a6b62806c;hpb=47f1bfca404ab6d61c7d384183d82a5f9c14d09b;p=u-boot diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c index ae471837fa..1212b72676 100644 --- a/drivers/serial/serial_lpuart.c +++ b/drivers/serial/serial_lpuart.c @@ -1,10 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2013 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ */ #include +#include +#include #include #include #include @@ -47,26 +48,75 @@ DECLARE_GLOBAL_DATA_PTR; -struct lpuart_fsl *base = (struct lpuart_fsl *)LPUART_BASE; +#define LPUART_FLAG_REGMAP_32BIT_REG BIT(0) +#define LPUART_FLAG_REGMAP_ENDIAN_BIG BIT(1) -#ifndef CONFIG_LPUART_32B_REG -static void lpuart_serial_setbrg(void) +enum lpuart_devtype { + DEV_VF610 = 1, + DEV_LS1021A, + DEV_MX7ULP +}; + +struct lpuart_serial_platdata { + void *reg; + enum lpuart_devtype devtype; + ulong flags; +}; + +static void lpuart_read32(u32 flags, u32 *addr, u32 *val) { - u32 clk = mxc_get_clock(MXC_UART_CLK); - u16 sbr; + if (flags & LPUART_FLAG_REGMAP_32BIT_REG) { + if (flags & LPUART_FLAG_REGMAP_ENDIAN_BIG) + *(u32 *)val = in_be32(addr); + else + *(u32 *)val = in_le32(addr); + } +} + +static void lpuart_write32(u32 flags, u32 *addr, u32 val) +{ + if (flags & LPUART_FLAG_REGMAP_32BIT_REG) { + if (flags & LPUART_FLAG_REGMAP_ENDIAN_BIG) + out_be32(addr, val); + else + out_le32(addr, val); + } +} + - if (!gd->baudrate) - gd->baudrate = CONFIG_BAUDRATE; +#ifndef CONFIG_SYS_CLK_FREQ +#define CONFIG_SYS_CLK_FREQ 0 +#endif + +u32 __weak get_lpuart_clk(void) +{ + return CONFIG_SYS_CLK_FREQ; +} + +static bool is_lpuart32(struct udevice *dev) +{ + struct lpuart_serial_platdata *plat = dev->platdata; - sbr = (u16)(clk / (16 * gd->baudrate)); + return plat->flags & LPUART_FLAG_REGMAP_32BIT_REG; +} + +static void _lpuart_serial_setbrg(struct lpuart_serial_platdata *plat, + int baudrate) +{ + struct lpuart_fsl *base = plat->reg; + u32 clk = get_lpuart_clk(); + u16 sbr; + + sbr = (u16)(clk / (16 * baudrate)); /* place adjustment later - n/32 BRFA */ __raw_writeb(sbr >> 8, &base->ubdh); __raw_writeb(sbr & 0xff, &base->ubdl); } -static int lpuart_serial_getc(void) +static int _lpuart_serial_getc(struct lpuart_serial_platdata *plat) { + struct lpuart_fsl *base = plat->reg; while (!(__raw_readb(&base->us1) & (US1_RDRF | US1_OR))) WATCHDOG_RESET(); @@ -75,10 +125,10 @@ static int lpuart_serial_getc(void) return __raw_readb(&base->ud); } -static void lpuart_serial_putc(const char c) +static void _lpuart_serial_putc(struct lpuart_serial_platdata *plat, + const char c) { - if (c == '\n') - serial_putc('\r'); + struct lpuart_fsl *base = plat->reg; while (!(__raw_readb(&base->us1) & US1_TDRE)) WATCHDOG_RESET(); @@ -87,8 +137,10 @@ static void lpuart_serial_putc(const char c) } /* Test whether a character is in the RX buffer */ -static int lpuart_serial_tstc(void) +static int _lpuart_serial_tstc(struct lpuart_serial_platdata *plat) { + struct lpuart_fsl *base = plat->reg; + if (__raw_readb(&base->urcfifo) == 0) return 0; @@ -99,8 +151,9 @@ static int lpuart_serial_tstc(void) * Initialise the serial port with the given baudrate. The settings * are always 8 data bits, no parity, 1 stop bit, no start bits. */ -static int lpuart_serial_init(void) +static int _lpuart_serial_init(struct lpuart_serial_platdata *plat) { + struct lpuart_fsl *base = (struct lpuart_fsl *)plat->reg; u8 ctrl; ctrl = __raw_readb(&base->uc2); @@ -118,65 +171,136 @@ static int lpuart_serial_init(void) __raw_writeb(CFIFO_TXFLUSH | CFIFO_RXFLUSH, &base->ucfifo); /* provide data bits, parity, stop bit, etc */ - serial_setbrg(); + _lpuart_serial_setbrg(plat, gd->baudrate); __raw_writeb(UC2_RE | UC2_TE, &base->uc2); return 0; } -static struct serial_device lpuart_serial_drv = { - .name = "lpuart_serial", - .start = lpuart_serial_init, - .stop = NULL, - .setbrg = lpuart_serial_setbrg, - .putc = lpuart_serial_putc, - .puts = default_serial_puts, - .getc = lpuart_serial_getc, - .tstc = lpuart_serial_tstc, -}; -#else -static void lpuart32_serial_setbrg(void) +static void _lpuart32_serial_setbrg_7ulp(struct lpuart_serial_platdata *plat, + int baudrate) { - u32 clk = CONFIG_SYS_CLK_FREQ; - u32 sbr; + struct lpuart_fsl_reg32 *base = plat->reg; + u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp; + u32 clk = get_lpuart_clk(); + + baud_diff = baudrate; + osr = 0; + sbr = 0; + + for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) { + tmp_sbr = (clk / (baudrate * tmp_osr)); + + if (tmp_sbr == 0) + tmp_sbr = 1; + + /*calculate difference in actual buad w/ current values */ + tmp_diff = (clk / (tmp_osr * tmp_sbr)); + tmp_diff = tmp_diff - baudrate; + + /* select best values between sbr and sbr+1 */ + if (tmp_diff > (baudrate - (clk / (tmp_osr * (tmp_sbr + 1))))) { + tmp_diff = baudrate - (clk / (tmp_osr * (tmp_sbr + 1))); + tmp_sbr++; + } + + if (tmp_diff <= baud_diff) { + baud_diff = tmp_diff; + osr = tmp_osr; + sbr = tmp_sbr; + } + } + + /* + * TODO: handle buadrate outside acceptable rate + * if (baudDiff > ((config->baudRate_Bps / 100) * 3)) + * { + * Unacceptable baud rate difference of more than 3% + * return kStatus_LPUART_BaudrateNotSupport; + * } + */ + tmp = in_le32(&base->baud); + + if ((osr > 3) && (osr < 8)) + tmp |= LPUART_BAUD_BOTHEDGE_MASK; + + tmp &= ~LPUART_BAUD_OSR_MASK; + tmp |= LPUART_BAUD_OSR(osr-1); + + tmp &= ~LPUART_BAUD_SBR_MASK; + tmp |= LPUART_BAUD_SBR(sbr); - if (!gd->baudrate) - gd->baudrate = CONFIG_BAUDRATE; + /* explicitly disable 10 bit mode & set 1 stop bit */ + tmp &= ~(LPUART_BAUD_M10_MASK | LPUART_BAUD_SBNS_MASK); - sbr = (clk / (16 * gd->baudrate)); + out_le32(&base->baud, tmp); +} + +static void _lpuart32_serial_setbrg(struct lpuart_serial_platdata *plat, + int baudrate) +{ + struct lpuart_fsl_reg32 *base = plat->reg; + u32 clk = get_lpuart_clk(); + u32 sbr; + + sbr = (clk / (16 * baudrate)); /* place adjustment later - n/32 BRFA */ - out_be32(&base->baud, sbr); + lpuart_write32(plat->flags, &base->baud, sbr); } -static int lpuart32_serial_getc(void) +static int _lpuart32_serial_getc(struct lpuart_serial_platdata *plat) { - u32 stat; + struct lpuart_fsl_reg32 *base = plat->reg; + u32 stat, val; - while (((stat = in_be32(&base->stat)) & STAT_RDRF) == 0) { - out_be32(&base->stat, STAT_FLAGS); + lpuart_read32(plat->flags, &base->stat, &stat); + while ((stat & STAT_RDRF) == 0) { + lpuart_write32(plat->flags, &base->stat, STAT_FLAGS); WATCHDOG_RESET(); + lpuart_read32(plat->flags, &base->stat, &stat); } - return in_be32(&base->data) & 0x3ff; + lpuart_read32(plat->flags, &base->data, &val); + + lpuart_read32(plat->flags, &base->stat, &stat); + if (stat & STAT_OR) + lpuart_write32(plat->flags, &base->stat, STAT_OR); + + return val & 0x3ff; } -static void lpuart32_serial_putc(const char c) +static void _lpuart32_serial_putc(struct lpuart_serial_platdata *plat, + const char c) { + struct lpuart_fsl_reg32 *base = plat->reg; + u32 stat; + if (c == '\n') serial_putc('\r'); - while (!(in_be32(&base->stat) & STAT_TDRE)) + while (true) { + lpuart_read32(plat->flags, &base->stat, &stat); + + if ((stat & STAT_TDRE)) + break; + WATCHDOG_RESET(); + } - out_be32(&base->data, c); + lpuart_write32(plat->flags, &base->data, c); } /* Test whether a character is in the RX buffer */ -static int lpuart32_serial_tstc(void) +static int _lpuart32_serial_tstc(struct lpuart_serial_platdata *plat) { - if ((in_be32(&base->water) >> 24) == 0) + struct lpuart_fsl_reg32 *base = plat->reg; + u32 water; + + lpuart_read32(plat->flags, &base->water, &water); + + if ((water >> 24) == 0) return 0; return 1; @@ -186,54 +310,150 @@ static int lpuart32_serial_tstc(void) * Initialise the serial port with the given baudrate. The settings * are always 8 data bits, no parity, 1 stop bit, no start bits. */ -static int lpuart32_serial_init(void) +static int _lpuart32_serial_init(struct lpuart_serial_platdata *plat) { - u8 ctrl; + struct lpuart_fsl_reg32 *base = (struct lpuart_fsl_reg32 *)plat->reg; + u32 ctrl; - ctrl = in_be32(&base->ctrl); + lpuart_read32(plat->flags, &base->ctrl, &ctrl); ctrl &= ~CTRL_RE; ctrl &= ~CTRL_TE; - out_be32(&base->ctrl, ctrl); + lpuart_write32(plat->flags, &base->ctrl, ctrl); - out_be32(&base->modir, 0); - out_be32(&base->fifo, ~(FIFO_TXFE | FIFO_RXFE)); + lpuart_write32(plat->flags, &base->modir, 0); + lpuart_write32(plat->flags, &base->fifo, ~(FIFO_TXFE | FIFO_RXFE)); - out_be32(&base->match, 0); + lpuart_write32(plat->flags, &base->match, 0); - /* provide data bits, parity, stop bit, etc */ - serial_setbrg(); + if (plat->devtype == DEV_MX7ULP) { + _lpuart32_serial_setbrg_7ulp(plat, gd->baudrate); + } else { + /* provide data bits, parity, stop bit, etc */ + _lpuart32_serial_setbrg(plat, gd->baudrate); + } - out_be32(&base->ctrl, CTRL_RE | CTRL_TE); + lpuart_write32(plat->flags, &base->ctrl, CTRL_RE | CTRL_TE); return 0; } -static struct serial_device lpuart32_serial_drv = { - .name = "lpuart32_serial", - .start = lpuart32_serial_init, - .stop = NULL, - .setbrg = lpuart32_serial_setbrg, - .putc = lpuart32_serial_putc, - .puts = default_serial_puts, - .getc = lpuart32_serial_getc, - .tstc = lpuart32_serial_tstc, -}; -#endif +static int lpuart_serial_setbrg(struct udevice *dev, int baudrate) +{ + struct lpuart_serial_platdata *plat = dev->platdata; + + if (is_lpuart32(dev)) { + if (plat->devtype == DEV_MX7ULP) + _lpuart32_serial_setbrg_7ulp(plat, baudrate); + else + _lpuart32_serial_setbrg(plat, baudrate); + } else { + _lpuart_serial_setbrg(plat, baudrate); + } + + return 0; +} -void lpuart_serial_initialize(void) +static int lpuart_serial_getc(struct udevice *dev) { -#ifdef CONFIG_LPUART_32B_REG - serial_register(&lpuart32_serial_drv); -#else - serial_register(&lpuart_serial_drv); -#endif + struct lpuart_serial_platdata *plat = dev->platdata; + + if (is_lpuart32(dev)) + return _lpuart32_serial_getc(plat); + + return _lpuart_serial_getc(plat); } -__weak struct serial_device *default_serial_console(void) +static int lpuart_serial_putc(struct udevice *dev, const char c) { -#ifdef CONFIG_LPUART_32B_REG - return &lpuart32_serial_drv; -#else - return &lpuart_serial_drv; -#endif + struct lpuart_serial_platdata *plat = dev->platdata; + + if (is_lpuart32(dev)) + _lpuart32_serial_putc(plat, c); + else + _lpuart_serial_putc(plat, c); + + return 0; +} + +static int lpuart_serial_pending(struct udevice *dev, bool input) +{ + struct lpuart_serial_platdata *plat = dev->platdata; + struct lpuart_fsl *reg = plat->reg; + struct lpuart_fsl_reg32 *reg32 = plat->reg; + u32 stat; + + if (is_lpuart32(dev)) { + if (input) { + return _lpuart32_serial_tstc(plat); + } else { + lpuart_read32(plat->flags, ®32->stat, &stat); + return stat & STAT_TDRE ? 0 : 1; + } + } + + if (input) + return _lpuart_serial_tstc(plat); + else + return __raw_readb(®->us1) & US1_TDRE ? 0 : 1; +} + +static int lpuart_serial_probe(struct udevice *dev) +{ + struct lpuart_serial_platdata *plat = dev->platdata; + + if (is_lpuart32(dev)) + return _lpuart32_serial_init(plat); + else + return _lpuart_serial_init(plat); +} + +static int lpuart_serial_ofdata_to_platdata(struct udevice *dev) +{ + struct lpuart_serial_platdata *plat = dev->platdata; + const void *blob = gd->fdt_blob; + int node = dev_of_offset(dev); + fdt_addr_t addr; + + addr = devfdt_get_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + plat->reg = (void *)addr; + plat->flags = dev_get_driver_data(dev); + + if (!fdt_node_check_compatible(blob, node, "fsl,ls1021a-lpuart")) + plat->devtype = DEV_LS1021A; + else if (!fdt_node_check_compatible(blob, node, "fsl,imx7ulp-lpuart")) + plat->devtype = DEV_MX7ULP; + else if (!fdt_node_check_compatible(blob, node, "fsl,vf610-lpuart")) + plat->devtype = DEV_VF610; + + return 0; } + +static const struct dm_serial_ops lpuart_serial_ops = { + .putc = lpuart_serial_putc, + .pending = lpuart_serial_pending, + .getc = lpuart_serial_getc, + .setbrg = lpuart_serial_setbrg, +}; + +static const struct udevice_id lpuart_serial_ids[] = { + { .compatible = "fsl,ls1021a-lpuart", .data = + LPUART_FLAG_REGMAP_32BIT_REG | LPUART_FLAG_REGMAP_ENDIAN_BIG }, + { .compatible = "fsl,imx7ulp-lpuart", + .data = LPUART_FLAG_REGMAP_32BIT_REG }, + { .compatible = "fsl,vf610-lpuart"}, + { } +}; + +U_BOOT_DRIVER(serial_lpuart) = { + .name = "serial_lpuart", + .id = UCLASS_SERIAL, + .of_match = lpuart_serial_ids, + .ofdata_to_platdata = lpuart_serial_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct lpuart_serial_platdata), + .probe = lpuart_serial_probe, + .ops = &lpuart_serial_ops, + .flags = DM_FLAG_PRE_RELOC, +};