X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fserial%2Fserial_mxc.c;h=4fd2b1dd054f39cf5e560b10e93708147be27815;hb=a5b9f8c8f07f2a901354a77c6131cb0429881bf8;hp=1563bb3665b671073d34fb4ae4e459c68542e183;hpb=312a6c016a2d81aa3fbc605f5c0c315b6a4e3464;p=u-boot

diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
index 1563bb3665..4fd2b1dd05 100644
--- a/drivers/serial/serial_mxc.c
+++ b/drivers/serial/serial_mxc.c
@@ -76,6 +76,7 @@
 #define  UFCR_RXTL_SHF   0       /* Receiver trigger level shift */
 #define  UFCR_RFDIV      (7<<7)  /* Reference freq divider mask */
 #define  UFCR_RFDIV_SHF  7      /* Reference freq divider shift */
+#define  UFCR_DCEDTE	 (1<<6)  /* DTE mode select */
 #define  UFCR_TXTL_SHF   10      /* Transmitter trigger level shift */
 #define  USR1_PARITYERR  (1<<15) /* Parity error interrupt flag */
 #define  USR1_RTSS	 (1<<14) /* RTS pin status */
@@ -107,6 +108,8 @@
 #define  UTS_RXFULL	 (1<<3)	 /* RxFIFO full */
 #define  UTS_SOFTRST	 (1<<0)	 /* Software reset */
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifndef CONFIG_DM_SERIAL
 
 #ifndef CONFIG_MXC_UART_BASE
@@ -134,8 +137,6 @@
 #define UBRC  0xac /* Baud Rate Count Register */
 #define UTS   0xb4 /* UART Test Register (mx31) */
 
-DECLARE_GLOBAL_DATA_PTR;
-
 #define TXTL  2 /* reset default */
 #define RXTL  1 /* reset default */
 #define RFDIV 4 /* divide input clock by 2 */
@@ -269,8 +270,13 @@ int mxc_serial_setbrg(struct udevice *dev, int baudrate)
 	struct mxc_serial_platdata *plat = dev->platdata;
 	struct mxc_uart *const uart = plat->reg;
 	u32 clk = imx_get_uartclk();
+	u32 tmp;
+
+	tmp = 4 << UFCR_RFDIV_SHF;
+	if (plat->use_dte)
+		tmp |= UFCR_DCEDTE;
+	writel(tmp, &uart->fcr);
 
-	writel(4 << 7, &uart->fcr); /* divide input clock by 2 */
 	writel(0xf, &uart->bir);
 	writel(clk / (2 * baudrate), &uart->bmr);
 
@@ -341,9 +347,37 @@ static const struct dm_serial_ops mxc_serial_ops = {
 	.setbrg = mxc_serial_setbrg,
 };
 
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+static int mxc_serial_ofdata_to_platdata(struct udevice *dev)
+{
+	struct mxc_serial_platdata *plat = dev->platdata;
+	fdt_addr_t addr;
+
+	addr = dev_get_addr(dev);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	plat->reg = (struct mxc_uart *)addr;
+
+	plat->use_dte = fdtdec_get_bool(gd->fdt_blob, dev->of_offset,
+					"fsl,dte-mode");
+	return 0;
+}
+
+static const struct udevice_id mxc_serial_ids[] = {
+	{ .compatible = "fsl,imx7d-uart" },
+	{ }
+};
+#endif
+
 U_BOOT_DRIVER(serial_mxc) = {
 	.name	= "serial_mxc",
 	.id	= UCLASS_SERIAL,
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+	.of_match = mxc_serial_ids,
+	.ofdata_to_platdata = mxc_serial_ofdata_to_platdata,
+	.platdata_auto_alloc_size = sizeof(struct mxc_serial_platdata),
+#endif
 	.probe = mxc_serial_probe,
 	.ops	= &mxc_serial_ops,
 	.flags = DM_FLAG_PRE_RELOC,