X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fserial%2Fserial_pl01x.c;h=23d9d839cbc1c249af6e0556ff11dbb8e03d4740;hb=bd650cd404b6dc870b6cc220025f35da4b31d0f4;hp=75eb6bd729e1614033f1bd110fb602358cfb5e46;hpb=6983951a612aeecd906521e31de83d7fae309950;p=u-boot diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c index 75eb6bd729..23d9d839cb 100644 --- a/drivers/serial/serial_pl01x.c +++ b/drivers/serial/serial_pl01x.c @@ -21,6 +21,8 @@ #include #include "serial_pl01x_internal.h" +DECLARE_GLOBAL_DATA_PTR; + #ifndef CONFIG_DM_SERIAL static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS; @@ -28,7 +30,6 @@ static enum pl01x_type pl01x_type __attribute__ ((section(".data"))); static struct pl01x_regs *base_regs __attribute__ ((section(".data"))); #define NUM_PORTS (sizeof(port)/sizeof(port[0])) -DECLARE_GLOBAL_DATA_PTR; #endif static int pl01x_putc(struct pl01x_regs *regs, char c) @@ -78,13 +79,6 @@ static int pl01x_generic_serial_init(struct pl01x_regs *regs, writel(0, ®s->pl010_cr); break; case TYPE_PL011: -#ifdef CONFIG_PL011_SERIAL_FLUSH_ON_INIT - /* Empty RX fifo if necessary */ - if (readl(®s->pl011_cr) & UART_PL011_CR_UARTEN) { - while (!(readl(®s->fr) & UART_PL01x_FR_RXFE)) - readl(®s->dr); - } -#endif /* disable everything */ writel(0, ®s->pl011_cr); break; @@ -95,7 +89,7 @@ static int pl01x_generic_serial_init(struct pl01x_regs *regs, return 0; } -static int set_line_control(struct pl01x_regs *regs) +static int pl011_set_line_control(struct pl01x_regs *regs) { unsigned int lcr; /* @@ -103,21 +97,6 @@ static int set_line_control(struct pl01x_regs *regs) * control register write */ lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN; -#ifdef CONFIG_PL011_SERIAL_RLCR - { - int i; - - /* - * Program receive line control register after waiting - * 10 bus cycles. Delay be writing to readonly register - * 10 times - */ - for (i = 0; i < 10; i++) - writel(lcr, ®s->fr); - - writel(lcr, ®s->pl011_rlcr); - } -#endif writel(lcr, ®s->pl011_lcrh); return 0; } @@ -129,12 +108,15 @@ static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type, case TYPE_PL010: { unsigned int divisor; + /* disable everything */ + writel(0, ®s->pl010_cr); + switch (baudrate) { case 9600: divisor = UART_PL010_BAUD_9600; break; case 19200: - divisor = UART_PL010_BAUD_9600; + divisor = UART_PL010_BAUD_19200; break; case 38400: divisor = UART_PL010_BAUD_38400; @@ -152,6 +134,12 @@ static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type, writel((divisor & 0xf00) >> 8, ®s->pl010_lcrm); writel(divisor & 0xff, ®s->pl010_lcrl); + /* + * Set line control for the PL010 to be 8 bits, 1 stop bit, + * no parity, fifo enabled + */ + writel(UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN, + ®s->pl010_lcrh); /* Finally, enable the UART */ writel(UART_PL010_CR_UARTEN, ®s->pl010_cr); break; @@ -178,7 +166,7 @@ static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type, writel(divider, ®s->pl011_ibrd); writel(fraction, ®s->pl011_fbrd); - set_line_control(regs); + pl011_set_line_control(regs); /* Finally, enable the UART */ writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | UART_PL011_CR_RXE | UART_PL011_CR_RTS, ®s->pl011_cr); @@ -285,29 +273,30 @@ __weak struct serial_device *default_serial_console(void) #ifdef CONFIG_DM_SERIAL -struct pl01x_priv { - struct pl01x_regs *regs; - enum pl01x_type type; -}; - static int pl01x_serial_setbrg(struct udevice *dev, int baudrate) { struct pl01x_serial_platdata *plat = dev_get_platdata(dev); struct pl01x_priv *priv = dev_get_priv(dev); - pl01x_generic_setbrg(priv->regs, priv->type, plat->clock, baudrate); + if (!plat->skip_init) { + pl01x_generic_setbrg(priv->regs, priv->type, plat->clock, + baudrate); + } return 0; } -static int pl01x_serial_probe(struct udevice *dev) +int pl01x_serial_probe(struct udevice *dev) { struct pl01x_serial_platdata *plat = dev_get_platdata(dev); struct pl01x_priv *priv = dev_get_priv(dev); priv->regs = (struct pl01x_regs *)plat->base; priv->type = plat->type; - return pl01x_generic_serial_init(priv->regs, priv->type); + if (!plat->skip_init) + return pl01x_generic_serial_init(priv->regs, priv->type); + else + return 0; } static int pl01x_serial_getc(struct udevice *dev) @@ -335,16 +324,44 @@ static int pl01x_serial_pending(struct udevice *dev, bool input) return fr & UART_PL01x_FR_TXFF ? 0 : 1; } -static const struct dm_serial_ops pl01x_serial_ops = { +const struct dm_serial_ops pl01x_serial_ops = { .putc = pl01x_serial_putc, .pending = pl01x_serial_pending, .getc = pl01x_serial_getc, .setbrg = pl01x_serial_setbrg, }; +#if CONFIG_IS_ENABLED(OF_CONTROL) +static const struct udevice_id pl01x_serial_id[] ={ + {.compatible = "arm,pl011", .data = TYPE_PL011}, + {.compatible = "arm,pl010", .data = TYPE_PL010}, + {} +}; + +int pl01x_serial_ofdata_to_platdata(struct udevice *dev) +{ + struct pl01x_serial_platdata *plat = dev_get_platdata(dev); + fdt_addr_t addr; + + addr = devfdt_get_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + plat->base = addr; + plat->clock = dev_read_u32_default(dev, "clock", 1); + plat->type = dev_get_driver_data(dev); + plat->skip_init = dev_read_bool(dev, "skip-init"); + + return 0; +} +#endif + U_BOOT_DRIVER(serial_pl01x) = { .name = "serial_pl01x", .id = UCLASS_SERIAL, + .of_match = of_match_ptr(pl01x_serial_id), + .ofdata_to_platdata = of_match_ptr(pl01x_serial_ofdata_to_platdata), + .platdata_auto_alloc_size = sizeof(struct pl01x_serial_platdata), .probe = pl01x_serial_probe, .ops = &pl01x_serial_ops, .flags = DM_FLAG_PRE_RELOC, @@ -352,3 +369,31 @@ U_BOOT_DRIVER(serial_pl01x) = { }; #endif + +#if defined(CONFIG_DEBUG_UART_PL010) || defined(CONFIG_DEBUG_UART_PL011) + +#include + +static void _debug_uart_init(void) +{ +#ifndef CONFIG_DEBUG_UART_SKIP_INIT + struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_DEBUG_UART_BASE; + enum pl01x_type type = CONFIG_IS_ENABLED(DEBUG_UART_PL011) ? + TYPE_PL011 : TYPE_PL010; + + pl01x_generic_serial_init(regs, type); + pl01x_generic_setbrg(regs, type, + CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE); +#endif +} + +static inline void _debug_uart_putc(int ch) +{ + struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_DEBUG_UART_BASE; + + pl01x_putc(regs, ch); +} + +DEBUG_UART_FUNCS + +#endif