X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fserial%2Fserial_sh.c;h=bfdb2ce77a3b9baea4e1e4f3a1182458102f57b0;hb=12304871bc7839145f2b4238923e9023616d7399;hp=ee44ba26445c356d91a078364b89dce487b561dd;hpb=4985ca5af3767ffe13ea96e1dc26f88c81084414;p=u-boot diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c index ee44ba2644..bfdb2ce77a 100644 --- a/drivers/serial/serial_sh.c +++ b/drivers/serial/serial_sh.c @@ -1,6 +1,6 @@ /* * SuperH SCIF device driver. - * Copyright (c) 2007 Nobuhiro Iwamatsu + * Copyright (c) 2007,2008 Nobuhiro Iwamatsu * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,160 +18,222 @@ */ #include +#include #include -#ifdef CFG_SCIF_CONSOLE +#if defined(CONFIG_CONS_SCIF0) +# define SCIF_BASE SCIF0_BASE +#elif defined(CONFIG_CONS_SCIF1) +# define SCIF_BASE SCIF1_BASE +#elif defined(CONFIG_CONS_SCIF2) +# define SCIF_BASE SCIF2_BASE +#elif defined(CONFIG_CONS_SCIF3) +# define SCIF_BASE SCIF3_BASE +#elif defined(CONFIG_CONS_SCIF4) +# define SCIF_BASE SCIF4_BASE +#elif defined(CONFIG_CONS_SCIF5) +# define SCIF_BASE SCIF5_BASE +#else +# error "Default SCIF doesn't set....." +#endif -#if defined (CONFIG_CONS_SCIF0) -#define SCIF_BASE SCIF0_BASE -#elif defined (CONFIG_CONS_SCIF1) -#define SCIF_BASE SCIF1_BASE +/* Base register */ +#define SCSMR (vu_short *)(SCIF_BASE + 0x0) +#define SCBRR (vu_char *)(SCIF_BASE + 0x4) +#define SCSCR (vu_short *)(SCIF_BASE + 0x8) +#define SCFCR (vu_short *)(SCIF_BASE + 0x18) +#define SCFDR (vu_short *)(SCIF_BASE + 0x1C) +#if defined(CONFIG_CPU_SH7720) || \ + (defined(CONFIG_CPU_SH7723) && defined(CONFIG_SCIF_A)) +# define SCFSR (vu_short *)(SCIF_BASE + 0x14) /* SCSSR */ +# define SCFTDR (vu_char *)(SCIF_BASE + 0x20) +# define SCFRDR (vu_char *)(SCIF_BASE + 0x24) #else -#error "Default SCIF doesn't set....." +# define SCFTDR (vu_char *)(SCIF_BASE + 0xC) +# define SCFSR (vu_short *)(SCIF_BASE + 0x10) +# define SCFRDR (vu_char *)(SCIF_BASE + 0x14) #endif -#define SCSMR (vu_short *)(SCIF_BASE + 0x0) -#define SCBRR (vu_char *)(SCIF_BASE + 0x4) -#define SCSCR (vu_short *)(SCIF_BASE + 0x8) -#define SCFTDR (vu_char *)(SCIF_BASE + 0xC) -#define SCFSR (vu_short *)(SCIF_BASE + 0x10) -#define SCFRDR (vu_char *)(SCIF_BASE + 0x14) -#define SCFCR (vu_short *)(SCIF_BASE + 0x18) -#define SCFDR (vu_short *)(SCIF_BASE + 0x1C) -#if defined(CONFIG_SH4A) -#define SCRFDR (vu_short *)(SCIF_BASE + 0x20) -#define SCSPTR (vu_short *)(SCIF_BASE + 0x24) -#define SCLSR (vu_short *)(SCIF_BASE + 0x28) -#define SCRER (vu_short *)(SCIF_BASE + 0x2C) -#elif defined (CONFIG_SH4) -#define SCSPTR (vu_short *)(SCIF_BASE + 0x20) -#define SCLSR (vu_short *)(SCIF_BASE + 0x24) -#elif defined (CONFIG_SH3) -#define SCLSR (vu_short *)(SCIF_BASE + 0x24) +#if defined(CONFIG_CPU_SH7780) || \ + defined(CONFIG_CPU_SH7785) +# define SCRFDR (vu_short *)(SCIF_BASE + 0x20) +# define SCSPTR (vu_short *)(SCIF_BASE + 0x24) +# define SCLSR (vu_short *)(SCIF_BASE + 0x28) +# define SCRER (vu_short *)(SCIF_BASE + 0x2C) +# define LSR_ORER 1 +# define FIFOLEVEL_MASK 0xFF +#elif defined(CONFIG_CPU_SH7763) +# if defined(CONFIG_CONS_SCIF2) +# define SCSPTR (vu_short *)(SCIF_BASE + 0x20) +# define SCLSR (vu_short *)(SCIF_BASE + 0x24) +# define LSR_ORER 1 +# define FIFOLEVEL_MASK 0x1F +# else +# define SCRFDR (vu_short *)(SCIF_BASE + 0x20) +# define SCSPTR (vu_short *)(SCIF_BASE + 0x24) +# define SCLSR (vu_short *)(SCIF_BASE + 0x28) +# define SCRER (vu_short *)(SCIF_BASE + 0x2C) +# define LSR_ORER 1 +# define FIFOLEVEL_MASK 0xFF +# endif +#elif defined(CONFIG_CPU_SH7723) +# if defined(CONFIG_SCIF_A) +# define SCLSR SCFSR +# define LSR_ORER 0x0200 +# define FIFOLEVEL_MASK 0x3F +#else +# define SCLSR (vu_short *)(SCIF_BASE + 0x24) +# define LSR_ORER 1 +# define FIFOLEVEL_MASK 0x1F +#endif +#elif defined(CONFIG_CPU_SH7750) || \ + defined(CONFIG_CPU_SH7751) || \ + defined(CONFIG_CPU_SH7722) || \ + defined(CONFIG_CPU_SH7203) +# define SCSPTR (vu_short *)(SCIF_BASE + 0x20) +# define SCLSR (vu_short *)(SCIF_BASE + 0x24) +# define LSR_ORER 1 +# define FIFOLEVEL_MASK 0x1F +#elif defined(CONFIG_CPU_SH7720) +# define SCLSR SCFSR +# define LSR_ORER 0x0200 +# define FIFOLEVEL_MASK 0x1F +#elif defined(CONFIG_CPU_SH7710) || \ + defined(CONFIG_CPU_SH7712) +# define SCLSR SCFSR /* SCSSR */ +# define LSR_ORER 1 +# define FIFOLEVEL_MASK 0x1F #endif -#define SCR_RE (1 << 4) -#define SCR_TE (1 << 5) -#define FCR_RFRST (1 << 1) /* RFCL */ -#define FCR_TFRST (1 << 2) /* TFCL */ -#define FSR_DR (1 << 0) -#define FSR_RDF (1 << 1) -#define FSR_FER (1 << 3) -#define FSR_BRK (1 << 4) -#define FSR_FER (1 << 3) -#define FSR_TEND (1 << 6) -#define FSR_ER (1 << 7) +/* SCBRR register value setting */ +#if defined(CONFIG_CPU_SH7720) +# define SCBRR_VALUE(bps, clk) (((clk * 2) + 16 * bps) / (32 * bps) - 1) +#elif defined(CONFIG_CPU_SH7723) && defined(CONFIG_SCIF_A) +/* SH7723 SCIFA use bus clock. So clock *2 */ +# define SCBRR_VALUE(bps, clk) (((clk * 2 * 2) + 16 * bps) / (32 * bps) - 1) +#else /* Generic SuperH */ +# define SCBRR_VALUE(bps, clk) ((clk + 16 * bps) / (32 * bps) - 1) +#endif + +#define SCR_RE (1 << 4) +#define SCR_TE (1 << 5) +#define FCR_RFRST (1 << 1) /* RFCL */ +#define FCR_TFRST (1 << 2) /* TFCL */ +#define FSR_DR (1 << 0) +#define FSR_RDF (1 << 1) +#define FSR_FER (1 << 3) +#define FSR_BRK (1 << 4) +#define FSR_FER (1 << 3) +#define FSR_TEND (1 << 6) +#define FSR_ER (1 << 7) /*----------------------------------------------------------------------*/ -void serial_setbrg (void) +void serial_setbrg(void) { DECLARE_GLOBAL_DATA_PTR; - int divisor = gd->baudrate * 32; - *SCBRR = (CONFIG_SYS_CLK_FREQ + (divisor / 2)) / - (gd->baudrate * 32) - 1; + writeb(SCBRR_VALUE(gd->baudrate, CONFIG_SYS_CLK_FREQ), SCBRR); } -int serial_init (void) +int serial_init(void) { - *SCSCR = (SCR_RE | SCR_TE); - *SCSMR = 0 ; - *SCSMR = 0; - *SCFCR = (FCR_RFRST | FCR_TFRST); - *SCFCR; - *SCFCR = 0; + writew((SCR_RE | SCR_TE), SCSCR); + writew(0, SCSMR); + writew(0, SCSMR); + writew((FCR_RFRST | FCR_TFRST), SCFCR); + readw(SCFCR); + writew(0, SCFCR); serial_setbrg(); return 0; } -static int serial_tx_fifo_level (void) -{ - return (*SCFDR >> 8) & 0x1F; -} - -static int serial_rx_fifo_level (void) +static int serial_rx_fifo_level(void) { - return (*SCFDR >> 0) & 0x1F; +#if defined(SCRFDR) + return (readw(SCRFDR) >> 0) & FIFOLEVEL_MASK; +#else + return (readw(SCFDR) >> 0) & FIFOLEVEL_MASK; +#endif } -void serial_raw_putc (const char c) +void serial_raw_putc(const char c) { unsigned int fsr_bits_to_clear; while (1) { - if (*SCFSR & FSR_TEND) { /* Tx fifo is empty */ + if (readw(SCFSR) & FSR_TEND) { /* Tx fifo is empty */ fsr_bits_to_clear = FSR_TEND; break; } } - *SCFTDR = c; + writeb(c, SCFTDR); if (fsr_bits_to_clear != 0) - *SCFSR &= ~fsr_bits_to_clear; + writew(readw(SCFSR) & ~fsr_bits_to_clear, SCFSR); } -void serial_putc (const char c) +void serial_putc(const char c) { if (c == '\n') - serial_raw_putc ('\r'); - serial_raw_putc (c); + serial_raw_putc('\r'); + serial_raw_putc(c); } -void serial_puts (const char *s) +void serial_puts(const char *s) { char c; while ((c = *s++) != 0) - serial_putc (c); + serial_putc(c); } -int serial_tstc (void) +int serial_tstc(void) { return serial_rx_fifo_level() ? 1 : 0; } -#define FSR_ERR_CLEAR 0x0063 -#define RDRF_CLEAR 0x00fc -#define LSR_ORER 1 -void handle_error( void ){ - - (void)*SCFSR ; - *SCFSR = FSR_ERR_CLEAR ; - (void)*SCLSR ; - *SCLSR = 0x00 ; +#define FSR_ERR_CLEAR 0x0063 +#define RDRF_CLEAR 0x00fc +void handle_error(void) +{ + readw(SCFSR); + writew(FSR_ERR_CLEAR, SCFSR); + readw(SCLSR); + writew(0x00, SCLSR); } -int serial_getc_check( void ){ +int serial_getc_check(void) +{ unsigned short status; - status = *SCFSR ; + status = readw(SCFSR); - if (status & (FSR_FER | FSR_FER | FSR_ER | FSR_BRK)) + if (status & (FSR_FER | FSR_ER | FSR_BRK)) handle_error(); - if( *SCLSR & LSR_ORER ) + if (readw(SCLSR) & LSR_ORER) handle_error(); - return (status & ( FSR_DR | FSR_RDF )); + return status & (FSR_DR | FSR_RDF); } -int serial_getc (void) +int serial_getc(void) { - unsigned short status ; + unsigned short status; char ch; - while(!serial_getc_check()); - ch = *SCFRDR; - status = *SCFSR ; + while (!serial_getc_check()) + ; - *SCFSR = RDRF_CLEAR ; + ch = readb(SCFRDR); + status = readw(SCFSR); + + writew(RDRF_CLEAR, SCFSR); if (status & (FSR_FER | FSR_FER | FSR_ER | FSR_BRK)) handle_error(); - if( *SCLSR & LSR_ORER ) + if (readw(SCLSR) & LSR_ORER) handle_error(); - return ch ; + return ch; } - -#endif /* CFG_SCIF_CONSOLE */