X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fserial%2Fserial_sh.h;h=fe8cde4dedb5ffe3ea9c33779841038cbc9e90d6;hb=64f41212d880f3d00c6994d973aadeec5bda1b65;hp=a6558af187d84794c5978823e39ed18f465652d2;hpb=48ca882c9f17365641ccb7dab164aaff0bc58e08;p=u-boot diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h index a6558af187..fe8cde4ded 100644 --- a/drivers/serial/serial_sh.h +++ b/drivers/serial/serial_sh.h @@ -143,7 +143,9 @@ struct uart_port { #elif defined(CONFIG_H8S2678) # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ # define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port)) -#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752) +#elif defined(CONFIG_CPU_SH7757) || \ + defined(CONFIG_CPU_SH7752) || \ + defined(CONFIG_CPU_SH7753) # define SCSPTR0 0xfe4b0020 # define SCSPTR1 0xfe4b0020 # define SCSPTR2 0xfe4b0020 @@ -224,7 +226,8 @@ struct uart_port { # define SCSPTR3 0xffc60020 /* 16 bit SCIF */ # define SCIF_ORER 0x0001 /* Overrun error bit */ # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ -#elif defined(CONFIG_R8A7790) +#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ + defined(CONFIG_R8A7794) # define SCIF_ORER 0x0001 # define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */ #else @@ -301,7 +304,7 @@ struct uart_port { /* SH7763 SCIF2 support */ # define SCIF2_RFDC_MASK 0x001f # define SCIF2_TXROOM_MAX 16 -#elif defined(CONFIG_R8A7790) +#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK) # define SCIF_RFDC_MASK 0x003f #else @@ -585,7 +588,8 @@ SCIF_FNS(SCSPTR, 0, 0, 0, 0) #else SCIF_FNS(SCSPTR, 0, 0, 0x20, 16) #endif -#if defined(CONFIG_R8A7790) +#if defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ + defined(CONFIG_R8A7794) SCIF_FNS(DL, 0, 0, 0x30, 16) SCIF_FNS(CKS, 0, 0, 0x34, 16) #endif @@ -730,9 +734,9 @@ static inline int scbrr_calc(struct uart_port port, int bps, int clk) #define SCBRR_VALUE(bps, clk) scbrr_calc(sh_sci, bps, clk) #elif defined(__H8300H__) || defined(__H8300S__) #define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1) -#elif defined(CONFIG_R8A7790) -#define SCBRR DL -#define SCBRR_VALUE(bps, clk) (clk / bps / 16) +#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) +#define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */ +#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) /* Internal Clock */ #else /* Generic SH */ #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) #endif