X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fspi%2Fbfin_spi.c;h=e080bec7052e523fd7c72dccfda5d5ec97ebb9bb;hb=5c877b1ae0a4219ed6bd8d32cf3f7106b81ecb3b;hp=2a72f99b2482ee278b3e5452830de3dd4e0f5d11;hpb=3bc8556f9b24af60dba2b55a0abb1182dff45ecc;p=u-boot

diff --git a/drivers/spi/bfin_spi.c b/drivers/spi/bfin_spi.c
index 2a72f99b24..e080bec705 100644
--- a/drivers/spi/bfin_spi.c
+++ b/drivers/spi/bfin_spi.c
@@ -1,7 +1,7 @@
 /*
  * Driver for Blackfin On-Chip SPI device
  *
- * Copyright (c) 2005-2008 Analog Devices Inc.
+ * Copyright (c) 2005-2010 Analog Devices Inc.
  *
  * Licensed under the GPL-2 or later.
  */
@@ -13,6 +13,9 @@
 #include <spi.h>
 
 #include <asm/blackfin.h>
+#include <asm/dma.h>
+#include <asm/gpio.h>
+#include <asm/portmux.h>
 #include <asm/mach-common/bits/spi.h>
 
 struct bfin_spi_slave {
@@ -33,69 +36,143 @@ MAKE_SPI_FUNC(SPI_BAUD, 0x14)
 
 #define to_bfin_spi_slave(s) container_of(s, struct bfin_spi_slave, slave)
 
-__attribute__((weak))
+#define gpio_cs(cs) ((cs) - MAX_CTRL_CS)
+#ifdef CONFIG_BFIN_SPI_GPIO_CS
+# define is_gpio_cs(cs) ((cs) > MAX_CTRL_CS)
+#else
+# define is_gpio_cs(cs) 0
+#endif
+
 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 {
-#if defined(__ADSPBF538__) || defined(__ADSPBF539__)
-	/* The SPI1/SPI2 buses are weird ... only 1 CS */
-	if (bus > 0 && cs != 1)
-		return 0;
-#endif
-	return (cs >= 1 && cs <= 7);
+	if (is_gpio_cs(cs))
+		return gpio_is_valid(gpio_cs(cs));
+	else
+		return (cs >= 1 && cs <= MAX_CTRL_CS);
 }
 
-__attribute__((weak))
 void spi_cs_activate(struct spi_slave *slave)
 {
 	struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
-	write_SPI_FLG(bss,
-		(read_SPI_FLG(bss) &
-		~((!bss->flg << 8) << slave->cs)) |
-		(1 << slave->cs));
+
+	if (is_gpio_cs(slave->cs)) {
+		unsigned int cs = gpio_cs(slave->cs);
+		gpio_set_value(cs, bss->flg);
+		debug("%s: SPI_CS_GPIO:%x\n", __func__, gpio_get_value(cs));
+	} else {
+		write_SPI_FLG(bss,
+			(read_SPI_FLG(bss) &
+			~((!bss->flg << 8) << slave->cs)) |
+			(1 << slave->cs));
+		debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
+	}
+
 	SSYNC();
-	debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
 }
 
-__attribute__((weak))
 void spi_cs_deactivate(struct spi_slave *slave)
 {
 	struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
-	u16 flg;
 
-	/* make sure we force the cs to deassert rather than let the
-	 * pin float back up.  otherwise, exact timings may not be
-	 * met some of the time leading to random behavior (ugh).
-	 */
-	flg = read_SPI_FLG(bss) | ((!bss->flg << 8) << slave->cs);
-	write_SPI_FLG(bss, flg);
-	SSYNC();
-	debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
+	if (is_gpio_cs(slave->cs)) {
+		unsigned int cs = gpio_cs(slave->cs);
+		gpio_set_value(cs, !bss->flg);
+		debug("%s: SPI_CS_GPIO:%x\n", __func__, gpio_get_value(cs));
+	} else {
+		u16 flg;
+
+		/* make sure we force the cs to deassert rather than let the
+		 * pin float back up.  otherwise, exact timings may not be
+		 * met some of the time leading to random behavior (ugh).
+		 */
+		flg = read_SPI_FLG(bss) | ((!bss->flg << 8) << slave->cs);
+		write_SPI_FLG(bss, flg);
+		SSYNC();
+		debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
+
+		flg &= ~(1 << slave->cs);
+		write_SPI_FLG(bss, flg);
+		debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
+	}
 
-	flg &= ~(1 << slave->cs);
-	write_SPI_FLG(bss, flg);
 	SSYNC();
-	debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
 }
 
 void spi_init()
 {
 }
 
+#ifdef SPI_CTL
+# define SPI0_CTL SPI_CTL
+#endif
+
+#define SPI_PINS(n) \
+	[n] = { 0, P_SPI##n##_SCK, P_SPI##n##_MISO, P_SPI##n##_MOSI, 0 }
+static unsigned short pins[][5] = {
+#ifdef SPI0_CTL
+	SPI_PINS(0),
+#endif
+#ifdef SPI1_CTL
+	SPI_PINS(1),
+#endif
+#ifdef SPI2_CTL
+	SPI_PINS(2),
+#endif
+};
+
+#define SPI_CS_PINS(n) \
+	[n] = { \
+		P_SPI##n##_SSEL1, P_SPI##n##_SSEL2, P_SPI##n##_SSEL3, \
+		P_SPI##n##_SSEL4, P_SPI##n##_SSEL5, P_SPI##n##_SSEL6, \
+		P_SPI##n##_SSEL7, \
+	}
+static const unsigned short cs_pins[][7] = {
+#ifdef SPI0_CTL
+	SPI_CS_PINS(0),
+#endif
+#ifdef SPI1_CTL
+	SPI_CS_PINS(1),
+#endif
+#ifdef SPI2_CTL
+	SPI_CS_PINS(2),
+#endif
+};
+
+void spi_set_speed(struct spi_slave *slave, uint hz)
+{
+	struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
+	ulong sclk;
+	u32 baud;
+
+	sclk = get_sclk();
+	baud = sclk / (2 * hz);
+	/* baud should be rounded up */
+	if (sclk % (2 * hz))
+		baud += 1;
+	if (baud < 2)
+		baud = 2;
+	else if (baud > (u16)-1)
+		baud = -1;
+	bss->baud = baud;
+}
+
 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 		unsigned int max_hz, unsigned int mode)
 {
 	struct bfin_spi_slave *bss;
 	u32 mmr_base;
-	u32 baud;
 
 	if (!spi_cs_is_valid(bus, cs))
 		return NULL;
 
+	if (bus >= ARRAY_SIZE(pins) || pins[bus] == NULL) {
+		debug("%s: invalid bus %u\n", __func__, bus);
+		return NULL;
+	}
 	switch (bus) {
-#ifdef SPI_CTL
-# define SPI0_CTL SPI_CTL
-#endif
+#ifdef SPI0_CTL
 		case 0: mmr_base = SPI0_CTL; break;
+#endif
 #ifdef SPI1_CTL
 		case 1: mmr_base = SPI1_CTL; break;
 #endif
@@ -105,12 +182,6 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 		default: return NULL;
 	}
 
-	baud = get_sclk() / (2 * max_hz);
-	if (baud < 2)
-		baud = 2;
-	else if (baud > (u16)-1)
-		baud = -1;
-
 	bss = malloc(sizeof(*bss));
 	if (!bss)
 		return NULL;
@@ -122,11 +193,11 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 	if (mode & SPI_CPHA) bss->ctl |= CPHA;
 	if (mode & SPI_CPOL) bss->ctl |= CPOL;
 	if (mode & SPI_LSB_FIRST) bss->ctl |= LSBF;
-	bss->baud = baud;
 	bss->flg = mode & SPI_CS_HIGH ? 1 : 0;
+	spi_set_speed(&bss->slave, max_hz);
 
 	debug("%s: bus:%i cs:%i mmr:%x ctl:%x baud:%i flg:%i\n", __func__,
-		bus, cs, mmr_base, bss->ctl, baud, bss->flg);
+		bus, cs, mmr_base, bss->ctl, bss->baud, bss->flg);
 
 	return &bss->slave;
 }
@@ -137,168 +208,21 @@ void spi_free_slave(struct spi_slave *slave)
 	free(bss);
 }
 
-static void spi_portmux(struct spi_slave *slave)
-{
-#if defined(__ADSPBF51x__)
-#define SET_MUX(port, mux, func) port##_mux = ((port##_mux & ~PORT_x_MUX_##mux##_MASK) | PORT_x_MUX_##mux##_FUNC_##func)
-	u16 f_mux = bfin_read_PORTF_MUX();
-	u16 f_fer = bfin_read_PORTF_FER();
-	u16 g_mux = bfin_read_PORTG_MUX();
-	u16 g_fer = bfin_read_PORTG_FER();
-	u16 h_mux = bfin_read_PORTH_MUX();
-	u16 h_fer = bfin_read_PORTH_FER();
-	switch (slave->bus) {
-	case 0:
-		/* set SCK/MISO/MOSI */
-		SET_MUX(g, 7, 1);
-		g_fer |= PG12 | PG13 | PG14;
-		switch (slave->cs) {
-			case 1: SET_MUX(f, 2, 1); f_fer |= PF7;  break;
-			case 2: /* see G above */ g_fer |= PG15; break;
-			case 3: SET_MUX(h, 1, 3); f_fer |= PH4;  break;
-			case 4: /* no muxing */   h_fer |= PH8;  break;
-			case 5: SET_MUX(g, 1, 3); h_fer |= PG3;  break;
-			case 6: /* no muxing */                  break;
-			case 7: /* no muxing */                  break;
-		}
-	case 1:
-		/* set SCK/MISO/MOSI */
-		SET_MUX(h, 0, 2);
-		h_fer |= PH1 | PH2 | PH3;
-		switch (slave->cs) {
-			case 1: SET_MUX(h, 2, 3); h_fer |= PH6;  break;
-			case 2: SET_MUX(f, 0, 3); f_fer |= PF0;  break;
-			case 3: SET_MUX(g, 0, 3); g_fer |= PG0;  break;
-			case 4: SET_MUX(f, 3, 3); f_fer |= PF8;  break;
-			case 5: SET_MUX(g, 6, 3); h_fer |= PG11; break;
-			case 6: /* no muxing */                  break;
-			case 7: /* no muxing */                  break;
-		}
-	}
-	bfin_write_PORTF_MUX(f_mux);
-	bfin_write_PORTF_FER(f_fer);
-	bfin_write_PORTG_MUX(g_mux);
-	bfin_write_PORTG_FER(g_fer);
-	bfin_write_PORTH_MUX(h_mux);
-	bfin_write_PORTH_FER(h_fer);
-#elif defined(__ADSPBF52x__)
-#define SET_MUX(port, mux, func) port##_mux = ((port##_mux & ~PORT_x_MUX_##mux##_MASK) | PORT_x_MUX_##mux##_FUNC_##func)
-	u16 f_mux = bfin_read_PORTF_MUX();
-	u16 f_fer = bfin_read_PORTF_FER();
-	u16 g_mux = bfin_read_PORTG_MUX();
-	u16 g_fer = bfin_read_PORTG_FER();
-	u16 h_mux = bfin_read_PORTH_MUX();
-	u16 h_fer = bfin_read_PORTH_FER();
-	/* set SCK/MISO/MOSI */
-	SET_MUX(g, 0, 3);
-	g_fer |= PG2 | PG3 | PG4;
-	switch (slave->cs) {
-		case 1: /* see G above */ g_fer |= PG1;  break;
-		case 2: SET_MUX(f, 4, 3); f_fer |= PF12; break;
-		case 3: SET_MUX(f, 4, 3); f_fer |= PF13; break;
-		case 4: SET_MUX(h, 1, 1); h_fer |= PH8;  break;
-		case 5: SET_MUX(h, 2, 1); h_fer |= PH9;  break;
-		case 6: SET_MUX(f, 1, 3); f_fer |= PF9;  break;
-		case 7: SET_MUX(f, 2, 3); f_fer |= PF10; break;
-	}
-	bfin_write_PORTF_MUX(f_mux);
-	bfin_write_PORTF_FER(f_fer);
-	bfin_write_PORTG_MUX(g_mux);
-	bfin_write_PORTG_FER(g_fer);
-	bfin_write_PORTH_MUX(h_mux);
-	bfin_write_PORTH_FER(h_fer);
-#elif defined(__ADSPBF534__) || defined(__ADSPBF536__) || defined(__ADSPBF537__)
-	u16 mux = bfin_read_PORT_MUX();
-	u16 f_fer = bfin_read_PORTF_FER();
-	/* set SCK/MISO/MOSI */
-	f_fer |= PF11 | PF12 | PF13;
-	switch (slave->cs) {
-		case 1: f_fer |= PF10; break;
-		case 2: mux |= PJSE; break;
-		case 3: mux |= PJSE; break;
-		case 4: mux |= PFS4E; f_fer |= PF6; break;
-		case 5: mux |= PFS5E; f_fer |= PF5; break;
-		case 6: mux |= PFS6E; f_fer |= PF4; break;
-		case 7: mux |= PJCE_SPI; break;
-	}
-	bfin_write_PORT_MUX(mux);
-	bfin_write_PORTF_FER(f_fer);
-#elif defined(__ADSPBF538__) || defined(__ADSPBF539__)
-	u16 fer, pins;
-	if (slave->bus == 1)
-		pins = PD0 | PD1 | PD2 | (slave->cs == 1 ? PD4 : 0);
-	else if (slave->bus == 2)
-		pins = PD5 | PD6 | PD7 | (slave->cs == 1 ? PD9 : 0);
-	else
-		pins = 0;
-	if (pins) {
-		fer = bfin_read_PORTDIO_FER();
-		fer &= ~pins;
-		bfin_write_PORTDIO_FER(fer);
-	}
-#elif defined(__ADSPBF54x__)
-#define DO_MUX(port, pin) \
-	mux = ((mux & ~PORT_x_MUX_##pin##_MASK) | PORT_x_MUX_##pin##_FUNC_1); \
-	fer |= P##port##pin;
-	u32 mux;
-	u16 fer;
-	switch (slave->bus) {
-	case 0:
-		mux = bfin_read_PORTE_MUX();
-		fer = bfin_read_PORTE_FER();
-		/* set SCK/MISO/MOSI */
-		DO_MUX(E, 0);
-		DO_MUX(E, 1);
-		DO_MUX(E, 2);
-		switch (slave->cs) {
-			case 1: DO_MUX(E, 4); break;
-			case 2: DO_MUX(E, 5); break;
-			case 3: DO_MUX(E, 6); break;
-		}
-		bfin_write_PORTE_MUX(mux);
-		bfin_write_PORTE_FER(fer);
-		break;
-	case 1:
-		mux = bfin_read_PORTG_MUX();
-		fer = bfin_read_PORTG_FER();
-		/* set SCK/MISO/MOSI */
-		DO_MUX(G, 8);
-		DO_MUX(G, 9);
-		DO_MUX(G, 10);
-		switch (slave->cs) {
-			case 1: DO_MUX(G, 5); break;
-			case 2: DO_MUX(G, 6); break;
-			case 3: DO_MUX(G, 7); break;
-		}
-		bfin_write_PORTG_MUX(mux);
-		bfin_write_PORTG_FER(fer);
-		break;
-	case 2:
-		mux = bfin_read_PORTB_MUX();
-		fer = bfin_read_PORTB_FER();
-		/* set SCK/MISO/MOSI */
-		DO_MUX(B, 12);
-		DO_MUX(B, 13);
-		DO_MUX(B, 14);
-		switch (slave->cs) {
-			case 1: DO_MUX(B, 9);  break;
-			case 2: DO_MUX(B, 10); break;
-			case 3: DO_MUX(B, 11); break;
-		}
-		bfin_write_PORTB_MUX(mux);
-		bfin_write_PORTB_FER(fer);
-		break;
-	}
-#endif
-}
-
 int spi_claim_bus(struct spi_slave *slave)
 {
 	struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
 
 	debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
 
-	spi_portmux(slave);
+	if (is_gpio_cs(slave->cs)) {
+		unsigned int cs = gpio_cs(slave->cs);
+		gpio_request(cs, "bfin-spi");
+		gpio_direction_output(cs, !bss->flg);
+		pins[slave->bus][0] = P_DONTCARE;
+	} else
+		pins[slave->bus][0] = cs_pins[slave->bus][slave->cs - 1];
+	peripheral_request_list(pins[slave->bus], "bfin-spi");
+
 	write_SPI_CTL(bss, bss->ctl);
 	write_SPI_BAUD(bss, bss->baud);
 	SSYNC();
@@ -309,11 +233,144 @@ int spi_claim_bus(struct spi_slave *slave)
 void spi_release_bus(struct spi_slave *slave)
 {
 	struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
+
 	debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
+
+	peripheral_free_list(pins[slave->bus]);
+	if (is_gpio_cs(slave->cs))
+		gpio_free(gpio_cs(slave->cs));
+
 	write_SPI_CTL(bss, 0);
 	SSYNC();
 }
 
+#ifdef __ADSPBF54x__
+# define SPI_DMA_BASE DMA4_NEXT_DESC_PTR
+#elif defined(__ADSPBF533__) || defined(__ADSPBF532__) || defined(__ADSPBF531__) || \
+      defined(__ADSPBF538__) || defined(__ADSPBF539__)
+# define SPI_DMA_BASE DMA5_NEXT_DESC_PTR
+#elif defined(__ADSPBF561__)
+# define SPI_DMA_BASE DMA2_4_NEXT_DESC_PTR
+#elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__) || \
+      defined(__ADSPBF52x__) || defined(__ADSPBF51x__)
+# define SPI_DMA_BASE DMA7_NEXT_DESC_PTR
+# elif defined(__ADSPBF50x__)
+# define SPI_DMA_BASE DMA6_NEXT_DESC_PTR
+#else
+# error "Please provide SPI DMA channel defines"
+#endif
+static volatile struct dma_register *dma = (void *)SPI_DMA_BASE;
+
+#ifndef CONFIG_BFIN_SPI_IDLE_VAL
+# define CONFIG_BFIN_SPI_IDLE_VAL 0xff
+#endif
+
+#ifdef CONFIG_BFIN_SPI_NO_DMA
+# define SPI_DMA 0
+#else
+# define SPI_DMA 1
+#endif
+
+static int spi_dma_xfer(struct bfin_spi_slave *bss, const u8 *tx, u8 *rx,
+			uint bytes)
+{
+	int ret = -1;
+	u16 ndsize, spi_config, dma_config;
+	struct dmasg dmasg[2];
+	const u8 *buf;
+
+	if (tx) {
+		debug("%s: doing half duplex TX\n", __func__);
+		buf = tx;
+		spi_config = TDBR_DMA;
+		dma_config = 0;
+	} else {
+		debug("%s: doing half duplex RX\n", __func__);
+		buf = rx;
+		spi_config = RDBR_DMA;
+		dma_config = WNR;
+	}
+
+	dmasg[0].start_addr = (unsigned long)buf;
+	dmasg[0].x_modify = 1;
+	dma_config |= WDSIZE_8 | DMAEN;
+	if (bytes <= 65536) {
+		blackfin_dcache_flush_invalidate_range(buf, buf + bytes);
+		ndsize = NDSIZE_5;
+		dmasg[0].cfg = NDSIZE_0 | dma_config | FLOW_STOP | DI_EN;
+		dmasg[0].x_count = bytes;
+	} else {
+		blackfin_dcache_flush_invalidate_range(buf, buf + 65536 - 1);
+		ndsize = NDSIZE_7;
+		dmasg[0].cfg = NDSIZE_5 | dma_config | FLOW_ARRAY | DMA2D;
+		dmasg[0].x_count = 0;	/* 2^16 */
+		dmasg[0].y_count = bytes >> 16;	/* count / 2^16 */
+		dmasg[0].y_modify = 1;
+		dmasg[1].start_addr = (unsigned long)(buf + (bytes & ~0xFFFF));
+		dmasg[1].cfg = NDSIZE_0 | dma_config | FLOW_STOP | DI_EN;
+		dmasg[1].x_count = bytes & 0xFFFF; /* count % 2^16 */
+		dmasg[1].x_modify = 1;
+	}
+
+	dma->cfg = 0;
+	dma->irq_status = DMA_DONE | DMA_ERR;
+	dma->curr_desc_ptr = dmasg;
+	write_SPI_CTL(bss, (bss->ctl & ~TDBR_CORE));
+	write_SPI_STAT(bss, -1);
+	SSYNC();
+
+	write_SPI_TDBR(bss, CONFIG_BFIN_SPI_IDLE_VAL);
+	dma->cfg = ndsize | FLOW_ARRAY | DMAEN;
+	write_SPI_CTL(bss, (bss->ctl & ~TDBR_CORE) | spi_config);
+	SSYNC();
+
+	/*
+	 * We already invalidated the first 64k,
+	 * now while we just wait invalidate the remaining part.
+	 * Its not likely that the DMA is going to overtake
+	 */
+	if (bytes > 65536)
+		blackfin_dcache_flush_invalidate_range(buf + 65536, buf + bytes);
+
+	while (!(dma->irq_status & DMA_DONE))
+		if (ctrlc())
+			goto done;
+
+	dma->cfg = 0;
+
+	ret = 0;
+ done:
+	write_SPI_CTL(bss, bss->ctl);
+	return ret;
+}
+
+static int spi_pio_xfer(struct bfin_spi_slave *bss, const u8 *tx, u8 *rx,
+			uint bytes)
+{
+	/* todo: take advantage of hardware fifos  */
+	while (bytes--) {
+		u8 value = (tx ? *tx++ : CONFIG_BFIN_SPI_IDLE_VAL);
+		debug("%s: tx:%x ", __func__, value);
+		write_SPI_TDBR(bss, value);
+		SSYNC();
+		while ((read_SPI_STAT(bss) & TXS))
+			if (ctrlc())
+				return -1;
+		while (!(read_SPI_STAT(bss) & SPIF))
+			if (ctrlc())
+				return -1;
+		while (!(read_SPI_STAT(bss) & RXS))
+			if (ctrlc())
+				return -1;
+		value = read_SPI_RDBR(bss);
+		if (rx)
+			*rx++ = value;
+		debug("rx:%x\n", value);
+	}
+
+	return 0;
+}
+
 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 		void *din, unsigned long flags)
 {
@@ -338,32 +395,11 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 	if (flags & SPI_XFER_BEGIN)
 		spi_cs_activate(slave);
 
-	/* todo: take advantage of hardware fifos and setup RX dma */
-	while (bytes--) {
-		u8 value = (tx ? *tx++ : 0);
-		debug("%s: tx:%x ", __func__, value);
-		write_SPI_TDBR(bss, value);
-		SSYNC();
-		while ((read_SPI_STAT(bss) & TXS))
-			if (ctrlc()) {
-				ret = -1;
-				goto done;
-			}
-		while (!(read_SPI_STAT(bss) & SPIF))
-			if (ctrlc()) {
-				ret = -1;
-				goto done;
-			}
-		while (!(read_SPI_STAT(bss) & RXS))
-			if (ctrlc()) {
-				ret = -1;
-				goto done;
-			}
-		value = read_SPI_RDBR(bss);
-		if (rx)
-			*rx++ = value;
-		debug("rx:%x\n", value);
-	}
+	/* TX DMA doesn't work quite right */
+	if (SPI_DMA && bytes > 6 && (!tx /*|| !rx*/))
+		ret = spi_dma_xfer(bss, tx, rx, bytes);
+	else
+		ret = spi_pio_xfer(bss, tx, rx, bytes);
 
  done:
 	if (flags & SPI_XFER_END)