X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fspi%2Fich.h;h=bd0a82080962ae41f42b4bab36cf7ef2db787359;hb=623f60198b38c4fdae596038cd5956e44b6224a4;hp=d2e4b8523bf6d442fb5d27101a6c0c83d3bcb40c;hpb=8b485ba12b0defa0c4ed3559789250238f8331a8;p=u-boot

diff --git a/drivers/spi/ich.h b/drivers/spi/ich.h
index d2e4b8523b..bd0a820809 100644
--- a/drivers/spi/ich.h
+++ b/drivers/spi/ich.h
@@ -6,6 +6,9 @@
  * This file is derived from the flashrom project.
  */
 
+#ifndef _ICH_H_
+#define _ICH_H_
+
 struct ich7_spi_regs {
 	uint16_t spis;
 	uint16_t spic;
@@ -19,36 +22,37 @@ struct ich7_spi_regs {
 } __packed;
 
 struct ich9_spi_regs {
-	uint32_t bfpr;			/* 0x00 */
+	uint32_t bfpr;		/* 0x00 */
 	uint16_t hsfs;
 	uint16_t hsfc;
 	uint32_t faddr;
 	uint32_t _reserved0;
-	uint32_t fdata[16];		/* 0x10 */
-	uint32_t frap;			/* 0x50 */
+	uint32_t fdata[16];	/* 0x10 */
+	uint32_t frap;		/* 0x50 */
 	uint32_t freg[5];
 	uint32_t _reserved1[3];
-	uint32_t pr[5];			/* 0x74 */
+	uint32_t pr[5];		/* 0x74 */
 	uint32_t _reserved2[2];
-	uint8_t ssfs;			/* 0x90 */
+	uint8_t ssfs;		/* 0x90 */
 	uint8_t ssfc[3];
-	uint16_t preop;			/* 0x94 */
+	uint16_t preop;		/* 0x94 */
 	uint16_t optype;
-	uint8_t opmenu[8];		/* 0x98 */
+	uint8_t opmenu[8];	/* 0x98 */
 	uint32_t bbar;
 	uint8_t _reserved3[12];
-	uint32_t fdoc;
+	uint32_t fdoc;		/* 0xb0 */
 	uint32_t fdod;
 	uint8_t _reserved4[8];
-	uint32_t afc;
+	uint32_t afc;		/* 0xc0 */
 	uint32_t lvscc;
 	uint32_t uvscc;
 	uint8_t _reserved5[4];
-	uint32_t fpb;
+	uint32_t fpb;		/* 0xd0 */
 	uint8_t _reserved6[28];
-	uint32_t srdl;
+	uint32_t srdl;		/* 0xf0 */
 	uint32_t srdc;
-	uint32_t srd;
+	uint32_t scs;
+	uint32_t bcr;
 } __packed;
 
 enum {
@@ -120,8 +124,38 @@ struct spi_trans {
 	uint32_t offset;
 };
 
-struct ich_spi_slave {
-	struct spi_slave slave;
+#define SPI_OPCODE_WREN		0x06
+#define SPI_OPCODE_FAST_READ	0x0b
+
+enum ich_version {
+	ICHV_7,
+	ICHV_9,
+};
+
+struct ich_spi_platdata {
+	enum ich_version ich_version;	/* Controller version, 7 or 9 */
+};
+
+struct ich_spi_priv {
+	int ichspi_lock;
+	int locked;
+	int opmenu;
+	int menubytes;
+	void *base;		/* Base of register set */
+	int preop;
+	int optype;
+	int addr;
+	int data;
+	unsigned databytes;
+	int status;
+	int control;
+	int bbar;
+	int bcr;
+	uint32_t *pr;		/* only for ich9 */
+	int speed;		/* pointer to speed control */
+	ulong max_speed;	/* Maximum bus speed in MHz */
+	ulong cur_speed;	/* Current bus speed */
 	struct spi_trans trans;	/* current transaction in progress */
-	int speed;		/* SPI speed in Hz */
 };
+
+#endif /* _ICH_H_ */