X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fspi%2Frk_spi.c;h=14437c0a9afe65808786fea09109f97dbef94680;hb=6189f76ae8fb3549349443d1d702d3d652d1244b;hp=3e44f1795e3ccbcfedb606ece22b01bebd07fde5;hpb=e160f7d430f163bc42757aff3bf2bcac0a459f02;p=u-boot diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c index 3e44f1795e..14437c0a9a 100644 --- a/drivers/spi/rk_spi.c +++ b/drivers/spi/rk_spi.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * spi driver for rockchip * @@ -5,8 +6,6 @@ * * (C) Copyright 2008-2013 Rockchip Electronics * Peter, Software Engineering, . - * - * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -22,8 +21,6 @@ #include #include "rk_spi.h" -DECLARE_GLOBAL_DATA_PTR; - /* Change to 1 to output registers at the start of each transaction */ #define DEBUG_RK_SPI 0 @@ -79,12 +76,31 @@ static void rkspi_enable_chip(struct rockchip_spi *regs, bool enable) static void rkspi_set_clk(struct rockchip_spi_priv *priv, uint speed) { - uint clk_div; + /* + * We should try not to exceed the speed requested by the caller: + * when selecting a divider, we need to make sure we round up. + */ + uint clk_div = DIV_ROUND_UP(priv->input_rate, speed); + + /* The baudrate register (BAUDR) is defined as a 32bit register where + * the upper 16bit are reserved and having 'Fsclk_out' in the lower + * 16bits with 'Fsclk_out' defined as follows: + * + * Fsclk_out = Fspi_clk/ SCKDV + * Where SCKDV is any even value between 2 and 65534. + */ + if (clk_div > 0xfffe) { + clk_div = 0xfffe; + debug("%s: can't divide down to %d Hz (actual will be %d Hz)\n", + __func__, speed, priv->input_rate / clk_div); + } + + /* Round up to the next even 16bit number */ + clk_div = (clk_div + 1) & 0xfffe; - clk_div = clk_get_divisor(priv->input_rate, speed); debug("spi speed %u, div %u\n", speed, clk_div); - writel(clk_div, &priv->regs->baudr); + clrsetbits_le32(&priv->regs->baudr, 0xffff, clk_div); priv->last_speed_hz = speed; } @@ -163,11 +179,9 @@ static int rockchip_spi_ofdata_to_platdata(struct udevice *bus) #if !CONFIG_IS_ENABLED(OF_PLATDATA) struct rockchip_spi_platdata *plat = dev_get_platdata(bus); struct rockchip_spi_priv *priv = dev_get_priv(bus); - const void *blob = gd->fdt_blob; - int node = dev_of_offset(bus); int ret; - plat->base = dev_get_addr(bus); + plat->base = dev_read_addr(bus); ret = clk_get_by_index(bus, 0, &priv->clk); if (ret < 0) { @@ -176,12 +190,13 @@ static int rockchip_spi_ofdata_to_platdata(struct udevice *bus) return ret; } - plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", - 50000000); - plat->deactivate_delay_us = fdtdec_get_int(blob, node, - "spi-deactivate-delay", 0); - plat->activate_delay_us = fdtdec_get_int(blob, node, - "spi-activate-delay", 0); + plat->frequency = + dev_read_u32_default(bus, "spi-max-frequency", 50000000); + plat->deactivate_delay_us = + dev_read_u32_default(bus, "spi-deactivate-delay", 0); + plat->activate_delay_us = + dev_read_u32_default(bus, "spi-activate-delay", 0); + debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n", __func__, (uint)plat->base, plat->frequency, plat->deactivate_delay_us); @@ -190,6 +205,34 @@ static int rockchip_spi_ofdata_to_platdata(struct udevice *bus) return 0; } +static int rockchip_spi_calc_modclk(ulong max_freq) +{ + /* + * While this is not strictly correct for the RK3368, as the + * GPLL will be 576MHz, things will still work, as the + * clk_set_rate(...) implementation in our clock-driver will + * chose the next closest rate not exceeding what we request + * based on the output of this function. + */ + + unsigned div; + const unsigned long gpll_hz = 594000000UL; + + /* + * We need to find an input clock that provides at least twice + * the maximum frequency and can be generated from the assumed + * speed of GPLL (594MHz) using an integer divider. + * + * To give us more achievable bitrates at higher speeds (these + * are generated by dividing by an even 16-bit integer from + * this frequency), we try to have an input frequency of at + * least 4x our max_freq. + */ + + div = DIV_ROUND_UP(gpll_hz, max_freq * 4); + return gpll_hz / div; +} + static int rockchip_spi_probe(struct udevice *bus) { struct rockchip_spi_platdata *plat = dev_get_platdata(bus); @@ -207,11 +250,13 @@ static int rockchip_spi_probe(struct udevice *bus) priv->last_transaction_us = timer_get_us(); priv->max_freq = plat->frequency; - /* - * Use 99 MHz as our clock since it divides nicely into 594 MHz which - * is the assumed speed for CLK_GENERAL. - */ - ret = clk_set_rate(&priv->clk, 99000000); + /* Clamp the value from the DTS against any hardware limits */ + if (priv->max_freq > ROCKCHIP_SPI_MAX_RATE) + priv->max_freq = ROCKCHIP_SPI_MAX_RATE; + + /* Find a module-input clock that fits with the max_freq setting */ + ret = clk_set_rate(&priv->clk, + rockchip_spi_calc_modclk(priv->max_freq)); if (ret < 0) { debug("%s: Failed to set clock: %d\n", __func__, ret); return ret; @@ -371,10 +416,10 @@ static int rockchip_spi_set_speed(struct udevice *bus, uint speed) { struct rockchip_spi_priv *priv = dev_get_priv(bus); - if (speed > ROCKCHIP_SPI_MAX_RATE) - return -EINVAL; + /* Clamp to the maximum frequency specified in the DTS */ if (speed > priv->max_freq) speed = priv->max_freq; + priv->speed_hz = speed; return 0; @@ -403,6 +448,8 @@ static const struct dm_spi_ops rockchip_spi_ops = { static const struct udevice_id rockchip_spi_ids[] = { { .compatible = "rockchip,rk3288-spi" }, + { .compatible = "rockchip,rk3368-spi" }, + { .compatible = "rockchip,rk3399-spi" }, { } };