X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fspi%2Fzynq_spi.c;h=d370e495cdff45ea36c41bdaea3593bc7644e76c;hb=f74dc51bcab924a30e41b33981a4f96af3f9dd57;hp=50fb1aa479060e643f69c529371de507473d9e2e;hpb=b1c82da266f534813558b3a8e5d53f9055c5872a;p=u-boot

diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c
index 50fb1aa479..d370e495cd 100644
--- a/drivers/spi/zynq_spi.c
+++ b/drivers/spi/zynq_spi.c
@@ -13,9 +13,12 @@
 #include <errno.h>
 #include <malloc.h>
 #include <spi.h>
+#include <fdtdec.h>
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* zynq spi register bit masks ZYNQ_SPI_<REG>_<BIT>_MASK */
 #define ZYNQ_SPI_CR_MSA_MASK		(1 << 15)	/* Manual start enb */
 #define ZYNQ_SPI_CR_MCS_MASK		(1 << 14)	/* Manual chip select */
@@ -63,22 +66,22 @@ struct zynq_spi_priv {
 	u32 freq;		/* required frequency */
 };
 
-static inline struct zynq_spi_regs *get_zynq_spi_regs(struct udevice *bus)
-{
-	if (bus->seq)
-		return (struct zynq_spi_regs *)ZYNQ_SPI_BASEADDR1;
-	else
-		return (struct zynq_spi_regs *)ZYNQ_SPI_BASEADDR0;
-}
-
 static int zynq_spi_ofdata_to_platdata(struct udevice *bus)
 {
 	struct zynq_spi_platdata *plat = bus->platdata;
+	const void *blob = gd->fdt_blob;
+	int node = bus->of_offset;
+
+	plat->regs = (struct zynq_spi_regs *)dev_get_addr(bus);
 
-	plat->regs = get_zynq_spi_regs(bus);
-	plat->frequency = 166666700;
+	/* FIXME: Use 250MHz as a suitable default */
+	plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
+					250000000);
 	plat->speed_hz = plat->frequency / 2;
 
+	debug("%s: regs=%p max-frequency=%d\n", __func__,
+	      plat->regs, plat->frequency);
+
 	return 0;
 }
 
@@ -269,7 +272,8 @@ static int zynq_spi_set_speed(struct udevice *bus, uint speed)
 	writel(confr, &regs->cr);
 	priv->freq = speed;
 
-	debug("zynq_spi_set_speed: regs=%p, mode=%d\n", priv->regs, priv->freq);
+	debug("zynq_spi_set_speed: regs=%p, speed=%d\n",
+	      priv->regs, priv->freq);
 
 	return 0;
 }
@@ -284,9 +288,9 @@ static int zynq_spi_set_mode(struct udevice *bus, uint mode)
 	confr = readl(&regs->cr);
 	confr &= ~(ZYNQ_SPI_CR_CPHA_MASK | ZYNQ_SPI_CR_CPOL_MASK);
 
-	if (priv->mode & SPI_CPHA)
+	if (mode & SPI_CPHA)
 		confr |= ZYNQ_SPI_CR_CPHA_MASK;
-	if (priv->mode & SPI_CPOL)
+	if (mode & SPI_CPOL)
 		confr |= ZYNQ_SPI_CR_CPOL_MASK;
 
 	writel(confr, &regs->cr);
@@ -306,7 +310,7 @@ static const struct dm_spi_ops zynq_spi_ops = {
 };
 
 static const struct udevice_id zynq_spi_ids[] = {
-	{ .compatible = "xlnx,zynq-spi" },
+	{ .compatible = "xlnx,zynq-spi-r1p6" },
 	{ }
 };