X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fsystemace.c;h=c9fd5f16701872cac07c4d4dacb7af11316aefc1;hb=fb05f6da35ea1c15c553abe6f23f656bf18dc5db;hp=8dd98d03fb04e6fe4df507aa751aa81de2958537;hpb=3a8ce9af6fcb5744a7851b4440c07688acc40844;p=u-boot diff --git a/drivers/systemace.c b/drivers/systemace.c index 8dd98d03fb..c9fd5f1670 100644 --- a/drivers/systemace.c +++ b/drivers/systemace.c @@ -53,44 +53,27 @@ * to be the base address for the chip, usually in the local * peripheral bus. */ -static unsigned ace_readw(unsigned offset) -{ #if (CFG_SYSTEMACE_WIDTH == 8) - u16 temp; - #if !defined(__BIG_ENDIAN) - temp = ((u16) readb(CFG_SYSTEMACE_BASE + offset) << 8); - temp |= (u16) readb(CFG_SYSTEMACE_BASE + offset + 1); +#define ace_readw(off) ((readb(CFG_SYSTEMACE_BASE+off)<<8) | \ + (readb(CFG_SYSTEMACE_BASE+off+1))) +#define ace_writew(val, off) {writeb(val>>8, CFG_SYSTEMACE_BASE+off); \ + writeb(val, CFG_SYSTEMACE_BASE+off+1);} #else - temp = (u16) readb(CFG_SYSTEMACE_BASE + offset); - temp |= ((u16) readb(CFG_SYSTEMACE_BASE + offset + 1) << 8); +#define ace_readw(off) ((readb(CFG_SYSTEMACE_BASE+off)) | \ + (readb(CFG_SYSTEMACE_BASE+off+1)<<8)) +#define ace_writew(val, off) {writeb(val, CFG_SYSTEMACE_BASE+off); \ + writeb(val>>8, CFG_SYSTEMACE_BASE+off+1);} #endif - return temp; #else - return readw(CFG_SYSTEMACE_BASE + offset); +#define ace_readw(off) (in16(CFG_SYSTEMACE_BASE+off)) +#define ace_writew(val, off) (out16(CFG_SYSTEMACE_BASE+off,val)) #endif -} - -static void ace_writew(unsigned val, unsigned offset) -{ -#if (CFG_SYSTEMACE_WIDTH == 8) -#if !defined(__BIG_ENDIAN) - writeb((u8) (val >> 8), CFG_SYSTEMACE_BASE + offset); - writeb((u8) val, CFG_SYSTEMACE_BASE + offset + 1); -#else - writeb((u8) val, CFG_SYSTEMACE_BASE + offset); - writeb((u8) (val >> 8), CFG_SYSTEMACE_BASE + offset + 1); -#endif -#else - writew(val, CFG_SYSTEMACE_BASE + offset); -#endif -} /* */ static unsigned long systemace_read(int dev, unsigned long start, - unsigned long blkcnt, - unsigned long *buffer); + unsigned long blkcnt, void *buffer); static block_dev_desc_t systemace_dev = { 0 }; @@ -136,6 +119,11 @@ block_dev_desc_t *systemace_get_dev(int dev) systemace_dev.removable = 1; systemace_dev.block_read = systemace_read; + /* + * Ensure the correct bus mode (8/16 bits) gets enabled + */ + ace_writew(CFG_SYSTEMACE_WIDTH == 8 ? 0 : 0x0001, 0); + init_part(&systemace_dev); } @@ -149,11 +137,11 @@ block_dev_desc_t *systemace_get_dev(int dev) * number of blocks read. A zero return indicates an error. */ static unsigned long systemace_read(int dev, unsigned long start, - unsigned long blkcnt, unsigned long *buffer) + unsigned long blkcnt, void *buffer) { int retry; unsigned blk_countdown; - unsigned char *dp = (unsigned char *)buffer; + unsigned char *dp = buffer; unsigned val; if (get_cf_lock() < 0) { @@ -214,7 +202,7 @@ static unsigned long systemace_read(int dev, unsigned long start, #endif /* Write LBA block address */ ace_writew((start >> 0) & 0xffff, 0x10); - ace_writew((start >> 16) & 0x00ff, 0x12); + ace_writew((start >> 16) & 0x0fff, 0x12); /* NOTE: in the Write Sector count below, a count of 0 causes a transfer of 256, so &0xff gives the right @@ -223,10 +211,16 @@ static unsigned long systemace_read(int dev, unsigned long start, /* Write sector count | ReadMemCardData. */ ace_writew((trans & 0xff) | 0x0300, 0x14); +/* + * For FPGA configuration via SystemACE is reset unacceptable + * CFGDONE bit in STATUSREG is not set to 1. + */ +#ifndef SYSTEMACE_CONFIG_FPGA /* Reset the configruation controller */ val = ace_readw(0x18); val |= 0x0080; ace_writew(val, 0x18); +#endif retry = trans * 16; while (retry > 0) {