X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fsystemace.c;h=c9fd5f16701872cac07c4d4dacb7af11316aefc1;hb=fb05f6da35ea1c15c553abe6f23f656bf18dc5db;hp=9502623a74116095c7b7afff39f7fb19f1af5b0e;hpb=958de0e22e408eadeffedcc130f69899c95de7c8;p=u-boot

diff --git a/drivers/systemace.c b/drivers/systemace.c
index 9502623a74..c9fd5f1670 100644
--- a/drivers/systemace.c
+++ b/drivers/systemace.c
@@ -56,24 +56,24 @@
 #if (CFG_SYSTEMACE_WIDTH == 8)
 #if !defined(__BIG_ENDIAN)
 #define ace_readw(off) ((readb(CFG_SYSTEMACE_BASE+off)<<8) | \
-                        (readb(CFG_SYSTEMACE_BASE+off+1)))
-#define ace_write(val, off) {writeb(val>>8, CFG_SYSTEMACE_BASE+off); \
-                             writeb(val, CFG_SYSTEMACE_BASE+off+1);}
+			(readb(CFG_SYSTEMACE_BASE+off+1)))
+#define ace_writew(val, off) {writeb(val>>8, CFG_SYSTEMACE_BASE+off); \
+			      writeb(val, CFG_SYSTEMACE_BASE+off+1);}
 #else
 #define ace_readw(off) ((readb(CFG_SYSTEMACE_BASE+off)) | \
-                        (readb(CFG_SYSTEMACE_BASE+off+1)<<8))
-#define ace_write(val, off) {writeb(val, CFG_SYSTEMACE_BASE+off); \
-                             writeb(val>>8, CFG_SYSTEMACE_BASE+off+1);}
+			(readb(CFG_SYSTEMACE_BASE+off+1)<<8))
+#define ace_writew(val, off) {writeb(val, CFG_SYSTEMACE_BASE+off); \
+			      writeb(val>>8, CFG_SYSTEMACE_BASE+off+1);}
 #endif
 #else
-#define ace_readw(off) (readw(CFG_SYSTEMACE_BASE+off))
-#define ace_writew(val, off) (writew(val, CFG_SYSTEMACE_BASE+off))
+#define ace_readw(off) (in16(CFG_SYSTEMACE_BASE+off))
+#define ace_writew(val, off) (out16(CFG_SYSTEMACE_BASE+off,val))
 #endif
 
 /* */
 
 static unsigned long systemace_read(int dev, unsigned long start,
-                                    unsigned long blkcnt, void *buffer);
+				    unsigned long blkcnt, void *buffer);
 
 static block_dev_desc_t systemace_dev = { 0 };
 
@@ -119,6 +119,11 @@ block_dev_desc_t *systemace_get_dev(int dev)
 		systemace_dev.removable = 1;
 		systemace_dev.block_read = systemace_read;
 
+		/*
+		 * Ensure the correct bus mode (8/16 bits) gets enabled
+		 */
+		ace_writew(CFG_SYSTEMACE_WIDTH == 8 ? 0 : 0x0001, 0);
+
 		init_part(&systemace_dev);
 
 	}
@@ -132,7 +137,7 @@ block_dev_desc_t *systemace_get_dev(int dev)
  * number of blocks read. A zero return indicates an error.
  */
 static unsigned long systemace_read(int dev, unsigned long start,
-                                    unsigned long blkcnt, void *buffer)
+				    unsigned long blkcnt, void *buffer)
 {
 	int retry;
 	unsigned blk_countdown;
@@ -197,7 +202,7 @@ static unsigned long systemace_read(int dev, unsigned long start,
 #endif
 		/* Write LBA block address */
 		ace_writew((start >> 0) & 0xffff, 0x10);
-		ace_writew((start >> 16) & 0x00ff, 0x12);
+		ace_writew((start >> 16) & 0x0fff, 0x12);
 
 		/* NOTE: in the Write Sector count below, a count of 0
 		   causes a transfer of 256, so &0xff gives the right
@@ -206,10 +211,16 @@ static unsigned long systemace_read(int dev, unsigned long start,
 		/* Write sector count | ReadMemCardData. */
 		ace_writew((trans & 0xff) | 0x0300, 0x14);
 
+/* 
+ * For FPGA configuration via SystemACE is reset unacceptable
+ * CFGDONE bit in STATUSREG is not set to 1.
+ */
+#ifndef SYSTEMACE_CONFIG_FPGA
 		/* Reset the configruation controller */
 		val = ace_readw(0x18);
 		val |= 0x0080;
 		ace_writew(val, 0x18);
+#endif
 
 		retry = trans * 16;
 		while (retry > 0) {