X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fusb%2Fhost%2Fehci-fsl.c;h=8f554649e15625406da818fbd97701ec4c2dd6d4;hb=85bafb6da4dddfffa78479aa49a72ae48578a4ce;hp=6cb4d986685c037757aca191dc9490e2a38c3a07;hpb=b71bf4add68a4a532196c0bead99ed1753014c2a;p=u-boot

diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 6cb4d98668..8f554649e1 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -14,7 +14,7 @@
 #include <asm/io.h>
 #include <usb/ehci-fsl.h>
 #include <hwconfig.h>
-#include <asm/fsl_errata.h>
+#include <fsl_usb.h>
 
 #include "ehci.h"
 
@@ -104,15 +104,20 @@ int ehci_hcd_init(int index, enum usb_init_type init,
 
 	if (!strncmp(phy_type, "utmi", 4)) {
 #if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
-		setbits_be32(&ehci->control, PHY_CLK_SEL_UTMI);
-		setbits_be32(&ehci->control, UTMI_PHY_EN);
+		clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
+				PHY_CLK_SEL_UTMI);
+		clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
+				UTMI_PHY_EN);
 		udelay(1000); /* delay required for PHY Clk to appear */
 #endif
 		out_le32(&(*hcor)->or_portsc[0], PORT_PTS_UTMI);
-		setbits_be32(&ehci->control, USB_EN);
+		clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
+				USB_EN);
 	} else {
-		setbits_be32(&ehci->control, PHY_CLK_SEL_ULPI);
-		clrsetbits_be32(&ehci->control, UTMI_PHY_EN, USB_EN);
+		clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
+				PHY_CLK_SEL_ULPI);
+		clrsetbits_be32(&ehci->control, UTMI_PHY_EN |
+				CONTROL_REGISTER_W1C_MASK, USB_EN);
 		udelay(1000); /* delay required for PHY Clk to appear */
 		if (!usb_phy_clk_valid(ehci))
 			return -EINVAL;
@@ -125,8 +130,7 @@ int ehci_hcd_init(int index, enum usb_init_type init,
 
 	in_le32(&ehci->usbmode);
 
-	if (SVR_SOC_VER(get_svr()) == SVR_T4240 &&
-	    IS_SVR_REV(get_svr(), 2, 0))
+	if (has_erratum_a007798())
 		set_txfifothresh(ehci, TXFIFOTHRESH);
 
 	return 0;