X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fusb%2Fhost%2Fehci-fsl.c;h=a43d37de0bc9ee507b5de5bcb2cc0bd882ca5d55;hb=79d867c2e683f7080a8724a54a4a12ac0ce1f837;hp=1ca7cf5d9b7911aac8e2bbc5c5ff7aefffe2e299;hpb=91d7746df89f858548fe535137b4b185a6a76d59;p=u-boot

diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 1ca7cf5d9b..a43d37de0b 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -12,11 +12,19 @@
 #include <pci.h>
 #include <usb.h>
 #include <asm/io.h>
-#include <usb/ehci-fsl.h>
+#include <usb/ehci-ci.h>
 #include <hwconfig.h>
+#include <fsl_usb.h>
+#include <fdt_support.h>
 
 #include "ehci.h"
 
+#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#endif
+
+static void set_txfifothresh(struct usb_ehci *, u32);
+
 /* Check USB PHY clock valid */
 static int usb_phy_clk_valid(struct usb_ehci *ehci)
 {
@@ -41,11 +49,23 @@ int ehci_hcd_init(int index, enum usb_init_type init,
 	struct usb_ehci *ehci = NULL;
 	const char *phy_type = NULL;
 	size_t len;
+	char current_usb_controller[5];
 #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 	char usb_phy[5];
 
 	usb_phy[0] = '\0';
 #endif
+	if (has_erratum_a007075()) {
+		/*
+		 * A 5ms delay is needed after applying soft-reset to the
+		 * controller to let external ULPI phy come out of reset.
+		 * This delay needs to be added before re-initializing
+		 * the controller after soft-resetting completes
+		 */
+		mdelay(5);
+	}
+	memset(current_usb_controller, '\0', 5);
+	snprintf(current_usb_controller, 4, "usb%d", index+1);
 
 	switch (index) {
 	case 0:
@@ -56,7 +76,7 @@ int ehci_hcd_init(int index, enum usb_init_type init,
 		break;
 	default:
 		printf("ERROR: wrong controller index!!\n");
-		break;
+		return -EINVAL;
 	};
 
 	*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
@@ -70,8 +90,9 @@ int ehci_hcd_init(int index, enum usb_init_type init,
 	out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB);
 
 	/* Init phy */
-	if (hwconfig_sub("usb1", "phy_type"))
-		phy_type = hwconfig_subarg("usb1", "phy_type", &len);
+	if (hwconfig_sub(current_usb_controller, "phy_type"))
+		phy_type = hwconfig_subarg(current_usb_controller,
+				"phy_type", &len);
 	else
 		phy_type = getenv("usb_phy_type");
 
@@ -88,15 +109,20 @@ int ehci_hcd_init(int index, enum usb_init_type init,
 
 	if (!strncmp(phy_type, "utmi", 4)) {
 #if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
-		setbits_be32(&ehci->control, PHY_CLK_SEL_UTMI);
-		setbits_be32(&ehci->control, UTMI_PHY_EN);
+		clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
+				PHY_CLK_SEL_UTMI);
+		clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
+				UTMI_PHY_EN);
 		udelay(1000); /* delay required for PHY Clk to appear */
 #endif
 		out_le32(&(*hcor)->or_portsc[0], PORT_PTS_UTMI);
-		setbits_be32(&ehci->control, USB_EN);
+		clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
+				USB_EN);
 	} else {
-		setbits_be32(&ehci->control, PHY_CLK_SEL_ULPI);
-		clrsetbits_be32(&ehci->control, UTMI_PHY_EN, USB_EN);
+		clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
+				PHY_CLK_SEL_ULPI);
+		clrsetbits_be32(&ehci->control, UTMI_PHY_EN |
+				CONTROL_REGISTER_W1C_MASK, USB_EN);
 		udelay(1000); /* delay required for PHY Clk to appear */
 		if (!usb_phy_clk_valid(ehci))
 			return -EINVAL;
@@ -109,6 +135,19 @@ int ehci_hcd_init(int index, enum usb_init_type init,
 
 	in_le32(&ehci->usbmode);
 
+	if (has_erratum_a007798())
+		set_txfifothresh(ehci, TXFIFOTHRESH);
+
+	if (has_erratum_a004477()) {
+		/*
+		 * When reset is issued while any ULPI transaction is ongoing
+		 * then it may result to corruption of ULPI Function Control
+		 * Register which eventually causes phy clock to enter low
+		 * power mode which stops the clock. Thus delay is required
+		 * before reset to let ongoing ULPI transaction complete.
+		 */
+		udelay(1);
+	}
 	return 0;
 }
 
@@ -120,3 +159,17 @@ int ehci_hcd_stop(int index)
 {
 	return 0;
 }
+
+/*
+ * Setting the value of TXFIFO_THRESH field in TXFILLTUNING register
+ * to counter DDR latencies in writing data into Tx buffer.
+ * This prevents Tx buffer from getting underrun
+ */
+static void set_txfifothresh(struct usb_ehci *ehci, u32 txfifo_thresh)
+{
+	u32 cmd;
+	cmd = ehci_readl(&ehci->txfilltuning);
+	cmd &= ~TXFIFO_THRESH_MASK;
+	cmd |= TXFIFO_THRESH(txfifo_thresh);
+	ehci_writel(&ehci->txfilltuning, cmd);
+}