X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fusb%2Fhost%2Fehci-fsl.c;h=a43d37de0bc9ee507b5de5bcb2cc0bd882ca5d55;hb=79d867c2e683f7080a8724a54a4a12ac0ce1f837;hp=8f554649e15625406da818fbd97701ec4c2dd6d4;hpb=85bafb6da4dddfffa78479aa49a72ae48578a4ce;p=u-boot

diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 8f554649e1..a43d37de0b 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -12,12 +12,17 @@
 #include <pci.h>
 #include <usb.h>
 #include <asm/io.h>
-#include <usb/ehci-fsl.h>
+#include <usb/ehci-ci.h>
 #include <hwconfig.h>
 #include <fsl_usb.h>
+#include <fdt_support.h>
 
 #include "ehci.h"
 
+#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#endif
+
 static void set_txfifothresh(struct usb_ehci *, u32);
 
 /* Check USB PHY clock valid */
@@ -71,7 +76,7 @@ int ehci_hcd_init(int index, enum usb_init_type init,
 		break;
 	default:
 		printf("ERROR: wrong controller index!!\n");
-		break;
+		return -EINVAL;
 	};
 
 	*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
@@ -133,6 +138,16 @@ int ehci_hcd_init(int index, enum usb_init_type init,
 	if (has_erratum_a007798())
 		set_txfifothresh(ehci, TXFIFOTHRESH);
 
+	if (has_erratum_a004477()) {
+		/*
+		 * When reset is issued while any ULPI transaction is ongoing
+		 * then it may result to corruption of ULPI Function Control
+		 * Register which eventually causes phy clock to enter low
+		 * power mode which stops the clock. Thus delay is required
+		 * before reset to let ongoing ULPI transaction complete.
+		 */
+		udelay(1);
+	}
 	return 0;
 }