X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fusb%2Fhost%2Fehci-mx6.c;h=2666351391431e091a761fb92f7879777bde2625;hb=cdc7732f3737f2bb97b77eb3d7c9da344bb73612;hp=0f94c8b6fb29d09d5ca39000f59e936ce0de6013;hpb=e38ff30a556fa02fd406cf73387e227b459cc49a;p=u-boot

diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index 0f94c8b6fb..2666351391 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -45,7 +45,10 @@
 #define ANADIG_USB2_PLL_480_CTRL_POWER		0x00001000
 #define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS	0x00000040
 
-
+#define USBNC_OFFSET		0x200
+#define USBNC_PHYSTATUS_ID_DIG	(1 << 4) /* otg_id status */
+#define USBNC_PHYCFG2_ACAENB	(1 << 4) /* otg_id detection enable */
+#define UCTRL_PM                (1 << 9) /* OTG Power Mask */
 #define UCTRL_OVER_CUR_POL	(1 << 8) /* OTG Polarity of Overcurrent */
 #define UCTRL_OVER_CUR_DIS	(1 << 7) /* Disable OTG Overcurrent Detection */
 
@@ -53,6 +56,7 @@
 #define UCMD_RUN_STOP           (1 << 0) /* controller run/stop */
 #define UCMD_RESET		(1 << 1) /* controller reset */
 
+#if defined(CONFIG_MX6)
 static const unsigned phy_bases[] = {
 	USB_PHY0_BASE_ADDR,
 	USB_PHY1_BASE_ADDR,
@@ -113,12 +117,39 @@ static void usb_power_config(int index)
 		     pll_480_ctrl_set);
 }
 
+static int wait_for_bit(u32 *reg, const u32 mask, bool set)
+{
+	u32 val;
+	const unsigned int timeout = 10000;
+	unsigned long start = get_timer(0);
+
+	while(1) {
+		val = readl(reg);
+		if (!set)
+			val = ~val;
+
+		if ((val & mask) == mask)
+			return 0;
+
+		if (get_timer(start) > timeout)
+			break;
+
+		udelay(1);
+	}
+
+	debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
+			__func__, reg, mask, set);
+
+	return -ETIMEDOUT;
+}
+
 /* Return 0 : host node, <>0 : device mode */
 static int usb_phy_enable(int index, struct usb_ehci *ehci)
 {
 	void __iomem *phy_reg;
 	void __iomem *phy_ctrl;
 	void __iomem *usb_cmd;
+	int ret;
 
 	if (index >= ARRAY_SIZE(phy_bases))
 		return 0;
@@ -129,12 +160,14 @@ static int usb_phy_enable(int index, struct usb_ehci *ehci)
 
 	/* Stop then Reset */
 	clrbits_le32(usb_cmd, UCMD_RUN_STOP);
-	while (readl(usb_cmd) & UCMD_RUN_STOP)
-		;
+	ret = wait_for_bit(usb_cmd, UCMD_RUN_STOP, 0);
+	if (ret)
+		return ret;
 
 	setbits_le32(usb_cmd, UCMD_RESET);
-	while (readl(usb_cmd) & UCMD_RESET)
-		;
+	ret = wait_for_bit(usb_cmd, UCMD_RESET, 0);
+	if (ret)
+		return ret;
 
 	/* Reset USBPHY module */
 	setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST);
@@ -153,6 +186,23 @@ static int usb_phy_enable(int index, struct usb_ehci *ehci)
 	return 0;
 }
 
+int usb_phy_mode(int port)
+{
+	void __iomem *phy_reg;
+	void __iomem *phy_ctrl;
+	u32 val;
+
+	phy_reg = (void __iomem *)phy_bases[port];
+	phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
+
+	val = readl(phy_ctrl);
+
+	if (val & USBPHY_CTRL_OTG_ID)
+		return USB_INIT_DEVICE;
+	else
+		return USB_INIT_HOST;
+}
+
 /* Base address for this IP block is 0x02184800 */
 struct usbnc_regs {
 	u32	ctrl[4];	/* otg/host1-3 */
@@ -161,12 +211,57 @@ struct usbnc_regs {
 	u32	otg_phy_ctrl_0;
 	u32	uh1_phy_ctrl_0;
 };
+#elif defined(CONFIG_MX7)
+struct usbnc_regs {
+	u32 ctrl1;
+	u32 ctrl2;
+	u32 reserve1[10];
+	u32 phy_cfg1;
+	u32 phy_cfg2;
+	u32 phy_status;
+	u32 reserve2[4];
+	u32 adp_cfg1;
+	u32 adp_cfg2;
+	u32 adp_status;
+};
+
+static void usb_power_config(int index)
+{
+	struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
+			(0x10000 * index) + USBNC_OFFSET);
+	void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2);
+
+	/* Enable usb_otg_id detection */
+	setbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB);
+}
+
+int usb_phy_mode(int port)
+{
+	struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
+			(0x10000 * port) + USBNC_OFFSET);
+	void __iomem *status = (void __iomem *)(&usbnc->phy_status);
+	u32 val;
+
+	val = readl(status);
+
+	if (val & USBNC_PHYSTATUS_ID_DIG)
+		return USB_INIT_DEVICE;
+	else
+		return USB_INIT_HOST;
+}
+#endif
 
 static void usb_oc_config(int index)
 {
+#if defined(CONFIG_MX6)
 	struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
 			USB_OTHERREGS_OFFSET);
 	void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]);
+#elif defined(CONFIG_MX7)
+	struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
+			(0x10000 * index) + USBNC_OFFSET);
+	void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1);
+#endif
 
 #if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2
 	/* mx6qarm2 seems to required a different setting*/
@@ -175,36 +270,54 @@ static void usb_oc_config(int index)
 	setbits_le32(ctrl, UCTRL_OVER_CUR_POL);
 #endif
 
+#if defined(CONFIG_MX6)
 	setbits_le32(ctrl, UCTRL_OVER_CUR_DIS);
+#elif defined(CONFIG_MX7)
+	setbits_le32(ctrl, UCTRL_OVER_CUR_DIS | UCTRL_PM);
+#endif
 }
 
-int usb_phy_mode(int port)
-{
-	void __iomem *phy_reg;
-	void __iomem *phy_ctrl;
-	u32 val;
-
-	phy_reg = (void __iomem *)phy_bases[port];
-	phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
-
-	val = readl(phy_ctrl);
-
-	if (val & USBPHY_CTRL_OTG_ID)
-		return USB_INIT_DEVICE;
-	else
-		return USB_INIT_HOST;
-}
-
+/**
+ * board_ehci_hcd_init - override usb phy mode
+ * @port:	usb host/otg port
+ *
+ * Target board specific, override usb_phy_mode.
+ * When usb-otg is used as usb host port, iomux pad usb_otg_id can be
+ * left disconnected in this case usb_phy_mode will not be able to identify
+ * the phy mode that usb port is used.
+ * Machine file overrides board_usb_phy_mode.
+ *
+ * Return: USB_INIT_DEVICE or USB_INIT_HOST
+ */
 int __weak board_usb_phy_mode(int port)
 {
 	return usb_phy_mode(port);
 }
 
+/**
+ * board_ehci_hcd_init - set usb vbus voltage
+ * @port:      usb otg port
+ *
+ * Target board specific, setup iomux pad to setup supply vbus voltage
+ * for usb otg port. Machine board file overrides board_ehci_hcd_init
+ *
+ * Return: 0 Success
+ */
 int __weak board_ehci_hcd_init(int port)
 {
 	return 0;
 }
 
+/**
+ * board_ehci_power - enables/disables usb vbus voltage
+ * @port:      usb otg port
+ * @on:        on/off vbus voltage
+ *
+ * Enables/disables supply vbus voltage for usb otg port.
+ * Machine board file overrides board_ehci_power
+ *
+ * Return: 0 Success
+ */
 int __weak board_ehci_power(int port, int on)
 {
 	return 0;
@@ -214,8 +327,13 @@ int ehci_hcd_init(int index, enum usb_init_type init,
 		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {
 	enum usb_init_type type;
+#if defined(CONFIG_MX6)
+	u32 controller_spacing = 0x200;
+#elif defined(CONFIG_MX7)
+	u32 controller_spacing = 0x10000;
+#endif
 	struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +
-		(0x200 * index));
+		(controller_spacing * index));
 
 	if (index > 3)
 		return -EINVAL;
@@ -227,8 +345,11 @@ int ehci_hcd_init(int index, enum usb_init_type init,
 
 	usb_power_config(index);
 	usb_oc_config(index);
+
+#if defined(CONFIG_MX6)
 	usb_internal_phy_clock_gate(index, 1);
 	usb_phy_enable(index, ehci);
+#endif
 	type = board_usb_phy_mode(index);
 
 	*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
@@ -241,6 +362,7 @@ int ehci_hcd_init(int index, enum usb_init_type init,
 		return -ENODEV;
 	if (type == USB_INIT_DEVICE)
 		return 0;
+
 	setbits_le32(&ehci->usbmode, CM_HOST);
 	writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
 	setbits_le32(&ehci->portsc, USB_EN);