X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fusb%2Fhost%2Fehci-mxc.c;h=a38bc9c1bb908c942fffc7e2cb556fcf488cd36d;hb=414e1660c8e898539411d92fbacdefc3e6bfbdfb;hp=8d7b3804fab4d91d2c7bc864ba4d484bed9215bc;hpb=17dd883c5b76bdade0f7a48f2eb02d918a5ebef9;p=u-boot

diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c
index 8d7b3804fa..a38bc9c1bb 100644
--- a/drivers/usb/host/ehci-mxc.c
+++ b/drivers/usb/host/ehci-mxc.c
@@ -20,15 +20,22 @@
 #include <common.h>
 #include <usb.h>
 #include <asm/io.h>
-#include <asm/arch/mx31-regs.h>
+#include <asm/arch/imx-regs.h>
 #include <usb/ehci-fsl.h>
 #include <errno.h>
 
 #include "ehci.h"
-#include "ehci-core.h"
 
 #define USBCTRL_OTGBASE_OFFSET	0x600
 
+#ifdef CONFIG_MX25
+#define MX25_USB_CTRL_IP_PUE_DOWN_BIT	(1<<6)
+#define MX25_USB_CTRL_HSTD_BIT		(1<<5)
+#define MX25_USB_CTRL_USBTE_BIT		(1<<4)
+#define MX25_USB_CTRL_OCPOL_OTG_BIT	(1<<3)
+#endif
+
+#ifdef CONFIG_MX31
 #define MX31_OTG_SIC_SHIFT	29
 #define MX31_OTG_SIC_MASK	(0x3 << MX31_OTG_SIC_SHIFT)
 #define MX31_OTG_PM_BIT		(1 << 24)
@@ -42,12 +49,19 @@
 #define MX31_H1_SIC_MASK	(0x3 << MX31_H1_SIC_SHIFT)
 #define MX31_H1_PM_BIT		(1 << 8)
 #define MX31_H1_DT_BIT		(1 << 4)
+#endif
 
 static int mxc_set_usbcontrol(int port, unsigned int flags)
 {
 	unsigned int v;
+
+#ifdef CONFIG_MX25
+	v = MX25_USB_CTRL_IP_PUE_DOWN_BIT | MX25_USB_CTRL_HSTD_BIT |
+		MX25_USB_CTRL_USBTE_BIT | MX25_USB_CTRL_OCPOL_OTG_BIT;
+#endif
+
 #ifdef CONFIG_MX31
-		v = readl(MX31_OTG_BASE_ADDR + USBCTRL_OTGBASE_OFFSET);
+		v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
 
 		switch (port) {
 		case 0:	/* OTG port */
@@ -85,36 +99,32 @@ static int mxc_set_usbcontrol(int port, unsigned int flags)
 		default:
 			return -EINVAL;
 		}
-
-		writel(v, MX31_OTG_BASE_ADDR +
-				     USBCTRL_OTGBASE_OFFSET);
 #endif
-		return 0;
+
+	writel(v, IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
+	return 0;
 }
 
-int ehci_hcd_init(void)
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {
-	u32 tmp;
 	struct usb_ehci *ehci;
+#ifdef CONFIG_MX31
 	struct clock_control_regs *sc_regs =
 		(struct clock_control_regs *)CCM_BASE;
 
-	tmp = __raw_readl(&sc_regs->ccmr);
+	__raw_readl(&sc_regs->ccmr);
 	__raw_writel(__raw_readl(&sc_regs->ccmr) | (1 << 9), &sc_regs->ccmr) ;
+#endif
 
 	udelay(80);
 
-	/* Take USB2 */
-	ehci = (struct usb_ehci *)(MX31_OTG_BASE_ADDR +
+	ehci = (struct usb_ehci *)(IMX_USB_BASE +
 		(0x200 * CONFIG_MXC_USB_PORT));
-	hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
-	hcor = (struct ehci_hcor *)((uint32_t) hccr +
-			HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+	*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
+	*hcor = (struct ehci_hcor *)((uint32_t) *hccr +
+			HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
 	setbits_le32(&ehci->usbmode, CM_HOST);
-	setbits_le32(&ehci->control, USB_EN);
-
 	__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
-
 	mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
 
 	udelay(10000);
@@ -126,7 +136,7 @@ int ehci_hcd_init(void)
  * Destroy the appropriate control structures corresponding
  * the the EHCI host controller.
  */
-int ehci_hcd_stop(void)
+int ehci_hcd_stop(int index)
 {
 	return 0;
 }