X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fusb%2Fhost%2Fxhci-fsl.c;h=05f09d7600b803a183709121eeed33d1d21bb840;hb=3861d784b1a470570a0098ac5c25d79e3073c0d9;hp=f624c9018371cbbb578002d43d2668bd2a0c648c;hpb=ba92ee06a5b792e5cbc144f95883cc54f4982255;p=u-boot

diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c
index f624c90183..05f09d7600 100644
--- a/drivers/usb/host/xhci-fsl.c
+++ b/drivers/usb/host/xhci-fsl.c
@@ -11,7 +11,6 @@
 #include <common.h>
 #include <usb.h>
 #include <asm-generic/errno.h>
-#include <asm/arch-ls102xa/immap_ls102xa.h>
 #include <linux/compat.h>
 #include <linux/usb/xhci-fsl.h>
 #include <linux/usb/dwc3.h>
@@ -28,23 +27,6 @@ __weak int __board_usb_init(int index, enum usb_init_type init)
 	return 0;
 }
 
-void usb_phy_reset(struct dwc3 *dwc3_reg)
-{
-	/* Assert USB3 PHY reset */
-	setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
-
-	/* Assert USB2 PHY reset */
-	setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
-
-	mdelay(200);
-
-	/* Clear USB3 PHY reset */
-	clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
-
-	/* Clear USB2 PHY reset */
-	clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
-}
-
 static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci)
 {
 	int ret = 0;
@@ -58,6 +40,9 @@ static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci)
 	/* We are hard-coding DWC3 core to Host Mode */
 	dwc3_set_mode(fsl_xhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
 
+	/* Set GFLADJ_30MHZ as 20h as per XHCI spec default value */
+	dwc3_set_fladj(fsl_xhci->dwc3_reg, GFLADJ_30MHZ_DEFAULT);
+
 	return ret;
 }
 
@@ -91,12 +76,12 @@ int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
 	}
 
 	*hccr = (struct xhci_hccr *)ctx->hcd;
-	*hcor = (struct xhci_hcor *)((uint32_t) *hccr
+	*hcor = (struct xhci_hcor *)((uintptr_t) *hccr
 				+ HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
 
-	debug("fsl-xhci: init hccr %x and hcor %x hc_length %d\n",
-	      (uint32_t)*hccr, (uint32_t)*hcor,
-	      (uint32_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
+	debug("fsl-xhci: init hccr %lx and hcor %lx hc_length %lx\n",
+	      (uintptr_t)*hccr, (uintptr_t)*hcor,
+	      (uintptr_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
 
 	return ret;
 }