X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fusb%2Fmusb%2Fmusb_core.h;h=e914369297047fcfcfa10ba0037fe30ab9820d83;hb=91dffb16ffd047458982f70f5cb18c864473a462;hp=47718764454c21ebe86a4a57c86ca61ee7100372;hpb=9bb47abf0d88e2dd151b36b39bf64c6593f417c8;p=u-boot

diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h
index 4771876445..e914369297 100644
--- a/drivers/usb/musb/musb_core.h
+++ b/drivers/usb/musb/musb_core.h
@@ -145,7 +145,7 @@ struct musb_regs {
 		struct musb_epN_regs epN;
 	} ep[16];
 
-} __attribute__((packed, aligned(32)));
+} __attribute__((packed, aligned(USB_DMA_MINALIGN)));
 #endif
 
 /*
@@ -357,7 +357,7 @@ extern struct musb_regs		*musbr;
 
 /* exported functions */
 extern void musb_start(void);
-extern void musb_configure_ep(struct musb_epinfo *epinfo, u8 cnt);
+extern void musb_configure_ep(const struct musb_epinfo *epinfo, u8 cnt);
 extern void write_fifo(u8 ep, u32 length, void *fifo_data);
 extern void read_fifo(u8 ep, u32 length, void *fifo_data);
 
@@ -369,6 +369,8 @@ extern void read_fifo(u8 ep, u32 length, void *fifo_data);
 # define readb(addr)     (u8)bfin_read16(addr)
 # undef  writeb
 # define writeb(b, addr) bfin_write16(addr, b)
+# undef MUSB_TXCSR_MODE /* not supported */
+# define MUSB_TXCSR_MODE 0
 /*
  * The USB PHY on current Blackfin processors is a UTMI+ level 2 PHY.
  * However, it has no ULPI support - so there are no registers at all.