X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fvideo%2Fct69000.c;h=0ed5f415f7c9690e715726984392e69657a55dc7;hb=d34d186ef9cf5a2e8030862cb5d281356046e6a1;hp=29d82e4c4351976f8b045b82674de3a4d15aa6a0;hpb=f743931f9b4d4e15c9bdfe726bef033ea1f1402c;p=u-boot

diff --git a/drivers/video/ct69000.c b/drivers/video/ct69000.c
index 29d82e4c43..0ed5f415f7 100644
--- a/drivers/video/ct69000.c
+++ b/drivers/video/ct69000.c
@@ -1,5 +1,5 @@
 /* ported from ctfb.c (linux kernel):
- * Created in Jan - July 2000 by Thomas Höhenleitner <th@visuelle-maschinen.de>
+ * Created in Jan - July 2000 by Thomas Höhenleitner <th@visuelle-maschinen.de>
  *
  * Ported to U-Boot:
  * (C) Copyright 2002 Denis Peter, MPL AG Switzerland
@@ -31,15 +31,15 @@
 #include <video_fb.h>
 #include "videomodes.h"
 
-#ifdef CONFIG_VIDEO_CT69000
-
 /* debug */
 #undef VGA_DEBUG
 #undef VGA_DUMP_REG
 #ifdef VGA_DEBUG
-#define	PRINTF(fmt,args...)	printf (fmt ,##args)
+#undef _DEBUG
+#define _DEBUG  1
 #else
-#define PRINTF(fmt,args...)
+#undef _DEBUG
+#define _DEBUG  0
 #endif
 
 /* Macros */
@@ -628,25 +628,25 @@ FindBestPQFittingMN (unsigned int p, unsigned int q, unsigned int mnmin,
 
 /* that is the hardware < 69000 we have to manage
  +---------+  +-------------------+  +----------------------+  +--+
- | REFCLK  |__|NTSC Divisor Select|__|FVCO Reference Divisor|__|÷N|__
- | 14.3MHz |  |(NTSCDS) (÷1, ÷5)  |  |Select (RDS) (÷1, ÷4) |  |  |  |
+ | REFCLK  |__|NTSC Divisor Select|__|FVCO Reference Divisor|__|÷N|__
+ | 14.3MHz |  |(NTSCDS) (÷1, ÷5)  |  |Select (RDS) (÷1, ÷4) |  |  |  |
  +---------+  +-------------------+  +----------------------+  +--+  |
   ___________________________________________________________________|
  |
  |                                    fvco                      fout
  | +--------+  +------------+  +-----+     +-------------------+   +----+
  +-| Phase  |__|Charge Pump |__| VCO |_____|Post Divisor (PD)  |___|CLK |--->
- +-| Detect |  |& Filter VCO|  |     |  |  |÷1, 2, 4, 8, 16, 32|   |    |
+ +-| Detect |  |& Filter VCO|  |     |  |  |÷1, 2, 4, 8, 16, 32|   |    |
  | +--------+  +------------+  +-----+  |  +-------------------+   +----+
  |                                      |
  |    +--+   +---------------+          |
- |____|÷M|___|VCO Loop Divide|__________|
-      |  |   |(VLD)(÷4, ÷16) |
+ |____|÷M|___|VCO Loop Divide|__________|
+      |  |   |(VLD)(÷4, ÷16) |
       +--+   +---------------+
 ****************************************************************************
   that is the hardware >= 69000 we have to manage
  +---------+  +--+
- | REFCLK  |__|÷N|__
+ | REFCLK  |__|÷N|__
  | 14.3MHz |  |  |  |
  +---------+  +--+  |
   __________________|
@@ -654,12 +654,12 @@ FindBestPQFittingMN (unsigned int p, unsigned int q, unsigned int mnmin,
  |                                    fvco                      fout
  | +--------+  +------------+  +-----+     +-------------------+   +----+
  +-| Phase  |__|Charge Pump |__| VCO |_____|Post Divisor (PD)  |___|CLK |--->
- +-| Detect |  |& Filter VCO|  |     |  |  |÷1, 2, 4, 8, 16, 32|   |    |
+ +-| Detect |  |& Filter VCO|  |     |  |  |÷1, 2, 4, 8, 16, 32|   |    |
  | +--------+  +------------+  +-----+  |  +-------------------+   +----+
  |                                      |
  |    +--+   +---------------+          |
- |____|÷M|___|VCO Loop Divide|__________|
-      |  |   |(VLD)(÷1, ÷4)  |
+ |____|÷M|___|VCO Loop Divide|__________|
+      |  |   |(VLD)(÷1, ÷4)  |
       +--+   +---------------+
 
 
@@ -742,7 +742,7 @@ FindAndSetPllParamIntoXrRegs (unsigned int pixelclock,
 	}
 	m += param->mn_diff;
 	n += param->mn_diff;
-	PRINTF ("VCO %d, pd %d, m %d n %d vld %d \n", fvco, pd, m, n, vld);
+	debug("VCO %d, pd %d, m %d n %d vld %d\n", fvco, pd, m, n, vld);
 	xr_cb = ((0x7 & PD) << 4) | (vld == param->vld_set ? 0x04 : 0);
 	/* All four of the registers used for dot clock 2 (XRC8 - XRCB) must be
 	 * written, and in order from XRC8 to XRCB, before the hardware will
@@ -753,7 +753,7 @@ FindAndSetPllParamIntoXrRegs (unsigned int pixelclock,
 	ctWrite_i (CT_XR_O, 0xca, 0);	/* because of a hw bug I guess, but we write */
 	ctWrite_i (CT_XR_O, 0xcb, xr_cb);	/* 0 to it for savety */
 	new_pixclock = ReadPixClckFromXrRegsBack (param);
-	PRINTF ("pixelclock.set = %d, pixelclock.real = %d \n",
+	debug("pixelclock.set = %d, pixelclock.real = %d\n",
 		pixelclock, new_pixclock);
 }
 
@@ -1109,7 +1109,7 @@ video_hw_init (void)
 		pGD->gdfIndex = GDF_24BIT_888RGB;
 		break;
 	}
-	pGD->isaBase = CFG_ISA_IO_BASE_ADDRESS;
+	pGD->isaBase = CONFIG_SYS_ISA_IO_BASE_ADDRESS;
 	pGD->pciBase = pci_mem_base;
 	pGD->frameAdrs = pci_mem_base;
 	pGD->memSize = chips_param->max_mem;
@@ -1121,7 +1121,7 @@ video_hw_init (void)
 		pGD->dprBase &= 0xfffff000;
 		pGD->dprBase += 0x00001000;
 	}
-	PRINTF ("Cursor Start %x Pattern Start %x\n", pGD->dprBase,
+	debug("Cursor Start %x Pattern Start %x\n", pGD->dprBase,
 		PATTERN_ADR);
 	pGD->vprBase = pci_mem_base;	/* Dummy */
 	pGD->cprBase = pci_mem_base;	/* Dummy */
@@ -1280,7 +1280,4 @@ video_hw_bitblt (unsigned int bpp,	/* bytes per pixel */
 	out32r (pGD->pciBase + BR08_o, (dim_y << 16) + dim_x);	/* start the BITBlt */
 	video_wait_bitblt (pGD->pciBase + BR04_o);
 }
-
-#endif				/* CONFIG_CT69000 */
-
 #endif				/* CONFIG_VIDEO */