X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fvideo%2Fipu_regs.h;h=982e25250970c45db57eeec2f82f55d70dc3e182;hb=4acb4d391f005c0c72f7b84041b3884e4260a5a4;hp=36f07bbee3368c01acf64003f415545c51bdaaf9;hpb=c163f4478ca72f51b28b55f74addc8fe029d7b83;p=u-boot

diff --git a/drivers/video/ipu_regs.h b/drivers/video/ipu_regs.h
index 36f07bbee3..982e252509 100644
--- a/drivers/video/ipu_regs.h
+++ b/drivers/video/ipu_regs.h
@@ -33,28 +33,38 @@
 #define IPU_DISP0_BASE		0x00000000
 #define IPU_MCU_T_DEFAULT	8
 #define IPU_DISP1_BASE		(IPU_MCU_T_DEFAULT << 25)
-#define IPU_CM_REG_BASE		0x1E000000
-#define IPU_STAT_REG_BASE	0x1E000200
-#define IPU_IDMAC_REG_BASE	0x1E008000
-#define IPU_ISP_REG_BASE	0x1E010000
-#define IPU_DP_REG_BASE		0x1E018000
-#define IPU_IC_REG_BASE		0x1E020000
-#define IPU_IRT_REG_BASE	0x1E028000
-#define IPU_CSI0_REG_BASE	0x1E030000
-#define IPU_CSI1_REG_BASE	0x1E038000
-#define IPU_DI0_REG_BASE	0x1E040000
-#define IPU_DI1_REG_BASE	0x1E048000
-#define IPU_SMFC_REG_BASE	0x1E050000
-#define IPU_DC_REG_BASE		0x1E058000
-#define IPU_DMFC_REG_BASE	0x1E060000
-#define IPU_CPMEM_REG_BASE	0x1F000000
-#define IPU_LUT_REG_BASE	0x1F020000
-#define IPU_SRM_REG_BASE	0x1F040000
-#define IPU_TPM_REG_BASE	0x1F060000
-#define IPU_DC_TMPL_REG_BASE	0x1F080000
-#define IPU_ISP_TBPR_REG_BASE	0x1F0C0000
-#define IPU_VDI_REG_BASE	0x1E068000
+#define IPU_CM_REG_BASE		0x00000000
+#define IPU_STAT_REG_BASE	0x00000200
+#define IPU_IDMAC_REG_BASE	0x00008000
+#define IPU_ISP_REG_BASE	0x00010000
+#define IPU_DP_REG_BASE		0x00018000
+#define IPU_IC_REG_BASE		0x00020000
+#define IPU_IRT_REG_BASE	0x00028000
+#define IPU_CSI0_REG_BASE	0x00030000
+#define IPU_CSI1_REG_BASE	0x00038000
+#define IPU_DI0_REG_BASE	0x00040000
+#define IPU_DI1_REG_BASE	0x00048000
+#define IPU_SMFC_REG_BASE	0x00050000
+#define IPU_DC_REG_BASE		0x00058000
+#define IPU_DMFC_REG_BASE	0x00060000
+#define IPU_VDI_REG_BASE	0x00680000
+#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
+#define IPU_CPMEM_REG_BASE	0x01000000
+#define IPU_LUT_REG_BASE	0x01020000
+#define IPU_SRM_REG_BASE	0x01040000
+#define IPU_TPM_REG_BASE	0x01060000
+#define IPU_DC_TMPL_REG_BASE	0x01080000
+#define IPU_ISP_TBPR_REG_BASE	0x010C0000
+#elif defined(CONFIG_MX6)
+#define IPU_CPMEM_REG_BASE	0x00100000
+#define IPU_LUT_REG_BASE	0x00120000
+#define IPU_SRM_REG_BASE	0x00140000
+#define IPU_TPM_REG_BASE	0x00160000
+#define IPU_DC_TMPL_REG_BASE	0x00180000
+#define IPU_ISP_TBPR_REG_BASE	0x001C0000
+#endif
 
+#define IPU_CTRL_BASE_ADDR	(IPU_SOC_BASE_ADDR + IPU_SOC_OFFSET)
 
 extern u32 *ipu_dc_tmpl_reg;
 
@@ -402,15 +412,15 @@ static inline struct ipu_dc_ch *dc_ch_offset(int ch)
 
 #define DP_REG			((struct ipu_dp *)(IPU_CTRL_BASE_ADDR + \
 				IPU_DP_REG_BASE))
-#define DP_COM_CONF(flow)	(&DP_REG->com_conf_sync)
-#define DP_GRAPH_WIND_CTRL(flow) (&DP_REG->graph_wind_ctrl_sync)
-#define DP_CSC_A_0(flow)	(&DP_REG->csca_sync[0])
-#define DP_CSC_A_1(flow)	(&DP_REG->csca_sync[1])
-#define DP_CSC_A_2(flow)	(&DP_REG->csca_sync[2])
-#define DP_CSC_A_3(flow)	(&DP_REG->csca_sync[3])
-
-#define DP_CSC_0(flow)		(&DP_REG->csc_sync[0])
-#define DP_CSC_1(flow)		(&DP_REG->csc_sync[1])
+#define DP_COM_CONF()		(&DP_REG->com_conf_sync)
+#define DP_GRAPH_WIND_CTRL()	(&DP_REG->graph_wind_ctrl_sync)
+#define DP_CSC_A_0()		(&DP_REG->csca_sync[0])
+#define DP_CSC_A_1()		(&DP_REG->csca_sync[1])
+#define DP_CSC_A_2()		(&DP_REG->csca_sync[2])
+#define DP_CSC_A_3()		(&DP_REG->csca_sync[3])
+
+#define DP_CSC_0()		(&DP_REG->csc_sync[0])
+#define DP_CSC_1()		(&DP_REG->csc_sync[1])
 
 /* DC template opcodes */
 #define WROD(lf)		(0x18 | (lf << 1))