X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fvideo%2Fipu_regs.h;h=c2c134a7de0738beca41c7b871c0869d5f6fe031;hb=5633a296ebb970d0a6be839fb37eaf8a11aa35f8;hp=a43aa03735b9e67b330450625a3fad6a74f9137e;hpb=b98b611502f5e0a85a1f8e15cf46c470cb105614;p=u-boot

diff --git a/drivers/video/ipu_regs.h b/drivers/video/ipu_regs.h
index a43aa03735..c2c134a7de 100644
--- a/drivers/video/ipu_regs.h
+++ b/drivers/video/ipu_regs.h
@@ -8,23 +8,7 @@
  *
  * (C) Copyright 2005-2009 Freescale Semiconductor, Inc.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #ifndef __IPU_REGS_INCLUDED__
@@ -55,7 +39,7 @@
 #define IPU_TPM_REG_BASE	0x01060000
 #define IPU_DC_TMPL_REG_BASE	0x01080000
 #define IPU_ISP_TBPR_REG_BASE	0x010C0000
-#elif defined(CONFIG_MX6Q)
+#elif defined(CONFIG_MX6)
 #define IPU_CPMEM_REG_BASE	0x00100000
 #define IPU_LUT_REG_BASE	0x00120000
 #define IPU_SRM_REG_BASE	0x00140000
@@ -187,7 +171,7 @@ struct ipu_cm {
 	u32 gpr;
 	u32 reserved0[26];
 	u32 ch_db_mode_sel[2];
-	u32 reserved1[16];
+	u32 reserved1[4];
 	u32 alt_ch_db_mode_sel[2];
 	u32 reserved2[2];
 	u32 ch_trb_mode_sel[2];
@@ -204,7 +188,7 @@ struct ipu_idmac {
 	u32 sub_addr[5];
 	u32 bndm_en[2];
 	u32 sc_cord[2];
-	u32 reserved[45];
+	u32 reserved[44];
 	u32 ch_busy[2];
 };
 
@@ -329,9 +313,12 @@ struct ipu_dmfc {
 
 #define IPU_STAT		((struct ipu_stat *)(IPU_CTRL_BASE_ADDR + \
 				IPU_STAT_REG_BASE))
+#define IPU_INT_STAT(n)		(&IPU_STAT->int_stat[(n) - 1])
 #define IPU_CHA_CUR_BUF(ch)	(&IPU_STAT->cur_buf[ch / 32])
 #define IPU_CHA_BUF0_RDY(ch)	(&IPU_STAT->ch_buf0_rdy[ch / 32])
 #define IPU_CHA_BUF1_RDY(ch)	(&IPU_STAT->ch_buf1_rdy[ch / 32])
+#define IPUIRQ_2_STATREG(irq)	(IPU_INT_STAT(1) + ((irq) / 32))
+#define IPUIRQ_2_MASK(irq)	(1UL << ((irq) & 0x1F))
 
 #define IPU_INT_CTRL(n)		(&IPU_CM_REG->int_ctrl[(n) - 1])