X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fvideo%2Fmb862xx.c;h=1c74e97c5e9d955de8b21bf2cb99735f9a877231;hb=6c2441c1d3f3ac11c7840aa1381a5beca68aafb3;hp=7bc3c9be9013668f0635e1a6f9461fd2b406bda4;hpb=e86528671ece6d5c1162656a37fc68a8e0bf67f8;p=u-boot diff --git a/drivers/video/mb862xx.c b/drivers/video/mb862xx.c index 7bc3c9be90..1c74e97c5e 100644 --- a/drivers/video/mb862xx.c +++ b/drivers/video/mb862xx.c @@ -2,23 +2,7 @@ * (C) Copyright 2007 * DENX Software Engineering, Anatolij Gustschin, agust@denx.de * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -70,29 +54,31 @@ unsigned int fr_div[] = { 0x00000f00, 0x00000900, 0x00000500 }; #define wr_io(addr, val) out_be32((volatile unsigned *)(addr), (val)) #endif -#define HOST_RD_REG(off) rd_io((dev->frameAdrs + 0x01fc0000 + (off))) -#define HOST_WR_REG(off, val) wr_io((dev->frameAdrs + 0x01fc0000 + (off)), \ +#define HOST_RD_REG(off) rd_io((dev->frameAdrs + GC_HOST_BASE + (off))) +#define HOST_WR_REG(off, val) wr_io((dev->frameAdrs + GC_HOST_BASE + (off)), \ (val)) -#define DISP_RD_REG(off) rd_io((dev->frameAdrs + 0x01fd0000 + (off))) -#define DISP_WR_REG(off, val) wr_io((dev->frameAdrs + 0x01fd0000 + (off)), \ +#define DISP_RD_REG(off) rd_io((dev->frameAdrs + GC_DISP_BASE + (off))) +#define DISP_WR_REG(off, val) wr_io((dev->frameAdrs + GC_DISP_BASE + (off)), \ (val)) #define DE_RD_REG(off) rd_io((dev->dprBase + (off))) #define DE_WR_REG(off, val) wr_io((dev->dprBase + (off)), (val)) #if defined(CONFIG_VIDEO_CORALP) -#define DE_WR_FIFO(val) wr_io((dev->dprBase + (0x8400)), (val)) +#define DE_WR_FIFO(val) wr_io((dev->dprBase + (GC_GEO_FIFO)), (val)) #else -#define DE_WR_FIFO(val) wr_io((dev->dprBase + (0x04a0)), (val)) +#define DE_WR_FIFO(val) wr_io((dev->dprBase + (GC_FIFO)), (val)) #endif -#define L0PAL_WR_REG(idx, val) wr_io((dev->frameAdrs + 0x01fd0400 + \ +#define L0PAL_WR_REG(idx, val) wr_io((dev->frameAdrs + \ + (GC_DISP_BASE | GC_L0PAL0) + \ ((idx) << 2)), (val)) +#if defined(CONFIG_VIDEO_MB862xx_ACCEL) static void gdc_sw_reset (void) { GraphicDevice *dev = &mb862xx; - HOST_WR_REG (0x002c, 0x00000001); + HOST_WR_REG (GC_SRST, 0x1); udelay (500); video_hw_init (); } @@ -107,10 +93,10 @@ static void de_wait (void) * Sync with software writes to framebuffer, * try to reset if engine locked */ - while (DE_RD_REG (0x0400) & 0x00000131) + while (DE_RD_REG (GC_CTR) & 0x00000131) if (lc-- < 0) { gdc_sw_reset (); - printf ("gdc reset done after drawing engine lock.\n"); + puts ("gdc reset done after drawing engine lock.\n"); break; } } @@ -121,13 +107,14 @@ static void de_wait_slots (int slots) int lc = 0x10000; /* Wait for free fifo slots */ - while (DE_RD_REG (0x0408) < slots) + while (DE_RD_REG (GC_IFCNT) < slots) if (lc-- < 0) { gdc_sw_reset (); - printf ("gdc reset done after drawing engine lock.\n"); + puts ("gdc reset done after drawing engine lock.\n"); break; } } +#endif #if !defined(CONFIG_VIDEO_CORALP) static void board_disp_init (void) @@ -143,28 +130,30 @@ static void board_disp_init (void) #endif /* - * Init drawing engine + * Init drawing engine if accel enabled. + * Also clears visible framebuffer. */ static void de_init (void) { GraphicDevice *dev = &mb862xx; +#if defined(CONFIG_VIDEO_MB862xx_ACCEL) int cf = (dev->gdfBytesPP == 1) ? 0x0000 : 0x8000; - dev->dprBase = dev->frameAdrs + 0x01ff0000; + dev->dprBase = dev->frameAdrs + GC_DRAW_BASE; /* Setup mode and fbbase, xres, fg, bg */ de_wait_slots (2); DE_WR_FIFO (0xf1010108); DE_WR_FIFO (cf | 0x0300); - DE_WR_REG (0x0440, 0x0000); - DE_WR_REG (0x0444, dev->winSizeX); - DE_WR_REG (0x0480, 0x0000); - DE_WR_REG (0x0484, 0x0000); + DE_WR_REG (GC_FBR, 0x0); + DE_WR_REG (GC_XRES, dev->winSizeX); + DE_WR_REG (GC_FC, 0x0); + DE_WR_REG (GC_BC, 0x0); /* Reset clipping */ - DE_WR_REG (0x0454, 0x0000); - DE_WR_REG (0x0458, dev->winSizeX); - DE_WR_REG (0x045c, 0x0000); - DE_WR_REG (0x0460, dev->winSizeY); + DE_WR_REG (GC_CXMIN, 0x0); + DE_WR_REG (GC_CXMAX, dev->winSizeX); + DE_WR_REG (GC_CYMIN, 0x0); + DE_WR_REG (GC_CYMAX, dev->winSizeY); /* Clear framebuffer using drawing engine */ de_wait_slots (3); @@ -173,16 +162,33 @@ static void de_init (void) DE_WR_FIFO (dev->winSizeY << 16 | dev->winSizeX); /* sync with SW access to framebuffer */ de_wait (); +#else + unsigned int i, *p; + + i = dev->winSizeX * dev->winSizeY; + p = (unsigned int *)dev->frameAdrs; + while (i--) + *p++ = 0; +#endif } #if defined(CONFIG_VIDEO_CORALP) +/* use CCF and MMR parameters for Coral-P Eval. Board as default */ +#ifndef CONFIG_SYS_MB862xx_CCF +#define CONFIG_SYS_MB862xx_CCF 0x00090000 +#endif +#ifndef CONFIG_SYS_MB862xx_MMR +#define CONFIG_SYS_MB862xx_MMR 0x11d7fa13 +#endif + unsigned int pci_video_init (void) { GraphicDevice *dev = &mb862xx; pci_dev_t devbusfn; + u16 device; if ((devbusfn = pci_find_devices (supported, 0)) < 0) { - printf ("PCI video controller not found!\n"); + puts("controller not present\n"); return 0; } @@ -193,16 +199,31 @@ unsigned int pci_video_init (void) dev->frameAdrs = pci_mem_to_phys (devbusfn, dev->frameAdrs); if (dev->frameAdrs == 0) { - printf ("PCI config: failed to get base address\n"); + puts ("PCI config: failed to get base address\n"); return 0; } dev->pciBase = dev->frameAdrs; - /* Setup clocks and memory mode for Coral-P Eval. Board */ - HOST_WR_REG (0x0038, 0x00090000); + puts("Coral-"); + + pci_read_config_word(devbusfn, PCI_DEVICE_ID, &device); + switch (device) { + case PCI_DEVICE_ID_CORAL_P: + puts("P\n"); + break; + case PCI_DEVICE_ID_CORAL_PA: + puts("PA\n"); + break; + default: + puts("Unknown\n"); + return 0; + } + + /* Setup clocks and memory mode for Coral-P(A) */ + HOST_WR_REG(GC_CCF, CONFIG_SYS_MB862xx_CCF); udelay (200); - HOST_WR_REG (0xfffc, 0x11d7fa13); + HOST_WR_REG(GC_MMR, CONFIG_SYS_MB862xx_MMR); udelay (100); return dev->frameAdrs; } @@ -222,8 +243,6 @@ unsigned int card_init (void) if (!pci_video_init ()) return 0; - printf ("CoralP\n"); - tmp = 0; videomode = 0x310; /* get video mode via environment */ @@ -251,7 +270,7 @@ unsigned int card_init (void) res_mode = (struct ctfb_res_modes *) &res_mode_init[vesa_modes[i].resindex]; if (vesa_modes[i].resindex > 2) { - printf ("\tUnsupported resolution, using default\n"); + puts ("\tUnsupported resolution, using default\n"); bpp = vesa_modes[1].bits_per_pixel; div = fr_div[1]; } @@ -295,52 +314,79 @@ unsigned int card_init (void) default: printf ("\t%d bpp configured, but only 8,15 and 16 supported\n", bpp); - printf ("\tSwitching back to 15bpp\n"); + puts ("\tfallback to 15bpp\n"); dev->gdfIndex = GDF_15BIT_555RGB; dev->gdfBytesPP = 2; } /* Setup dot clock (internal pll, division rate) */ - DISP_WR_REG (0x0100, div); + DISP_WR_REG (GC_DCM1, div); /* L0 init */ cf = (dev->gdfBytesPP == 1) ? 0x00000000 : 0x80000000; - DISP_WR_REG (0x0020, ((dev->winSizeX * dev->gdfBytesPP) / 64) << 16 | + DISP_WR_REG (GC_L0M, ((dev->winSizeX * dev->gdfBytesPP) / 64) << 16 | (dev->winSizeY - 1) | cf); - DISP_WR_REG (0x0024, 0x00000000); - DISP_WR_REG (0x0028, 0x00000000); - DISP_WR_REG (0x002c, 0x00000000); - DISP_WR_REG (0x0110, 0x00000000); - DISP_WR_REG (0x0114, 0x00000000); - DISP_WR_REG (0x0118, (dev->winSizeY - 1) << 16 | dev->winSizeX); + DISP_WR_REG (GC_L0OA0, 0x0); + DISP_WR_REG (GC_L0DA0, 0x0); + DISP_WR_REG (GC_L0DY_L0DX, 0x0); + DISP_WR_REG (GC_L0EM, 0x0); + DISP_WR_REG (GC_L0WY_L0WX, 0x0); + DISP_WR_REG (GC_L0WH_L0WW, (dev->winSizeY - 1) << 16 | dev->winSizeX); /* Display timing init */ - DISP_WR_REG (0x0004, (dev->winSizeX + - res_mode->left_margin + - res_mode->right_margin + - res_mode->hsync_len - 1) << 16); - DISP_WR_REG (0x0008, (dev->winSizeX - 1) << 16 | (dev->winSizeX - 1)); - DISP_WR_REG (0x000c, (res_mode->vsync_len - 1) << 24 | - (res_mode->hsync_len - 1) << 16 | - (dev->winSizeX + res_mode->right_margin - 1)); - DISP_WR_REG (0x0010, (dev->winSizeY + res_mode->lower_margin + - res_mode->upper_margin + - res_mode->vsync_len - 1) << 16); - DISP_WR_REG (0x0014, (dev->winSizeY-1) << 16 | - (dev->winSizeY + res_mode->lower_margin - 1)); - DISP_WR_REG (0x0018, 0x00000000); - DISP_WR_REG (0x001c, dev->winSizeY << 16 | dev->winSizeX); + DISP_WR_REG (GC_HTP_A, (dev->winSizeX + + res_mode->left_margin + + res_mode->right_margin + + res_mode->hsync_len - 1) << 16); + DISP_WR_REG (GC_HDB_HDP_A, (dev->winSizeX - 1) << 16 | + (dev->winSizeX - 1)); + DISP_WR_REG (GC_VSW_HSW_HSP_A, (res_mode->vsync_len - 1) << 24 | + (res_mode->hsync_len - 1) << 16 | + (dev->winSizeX + + res_mode->right_margin - 1)); + DISP_WR_REG (GC_VTR_A, (dev->winSizeY + res_mode->lower_margin + + res_mode->upper_margin + + res_mode->vsync_len - 1) << 16); + DISP_WR_REG (GC_VDP_VSP_A, (dev->winSizeY-1) << 16 | + (dev->winSizeY + + res_mode->lower_margin - 1)); + DISP_WR_REG (GC_WY_WX, 0x0); + DISP_WR_REG (GC_WH_WW, dev->winSizeY << 16 | dev->winSizeX); /* Display enable, L0 layer */ - DISP_WR_REG (0x0100, 0x80010000 | div); + DISP_WR_REG (GC_DCM1, 0x80010000 | div); return dev->frameAdrs; } #endif + +#if !defined(CONFIG_VIDEO_CORALP) +int mb862xx_probe(unsigned int addr) +{ + GraphicDevice *dev = &mb862xx; + unsigned int reg; + + dev->frameAdrs = addr; + dev->dprBase = dev->frameAdrs + GC_DRAW_BASE; + + /* Try to access GDC ID/Revision registers */ + reg = HOST_RD_REG (GC_CID); + reg = HOST_RD_REG (GC_CID); + if (reg == 0x303) { + reg = DE_RD_REG(GC_REV); + reg = DE_RD_REG(GC_REV); + if ((reg & ~0xff) == 0x20050100) + return MB862XX_TYPE_LIME; + } + + return 0; +} +#endif + void *video_hw_init (void) { GraphicDevice *dev = &mb862xx; - printf ("Video: Fujitsu "); + puts ("Video: Fujitsu "); memset (dev, 0, sizeof (GraphicDevice)); @@ -353,10 +399,18 @@ void *video_hw_init (void) * retrieve base address */ if ((dev->frameAdrs = board_video_init ()) == 0) { - printf ("Controller not found!\n"); + puts ("Controller not found!\n"); return NULL; - } else - printf ("Lime\n"); + } else { + puts ("Lime\n"); + + /* Set Change of Clock Frequency Register */ + HOST_WR_REG (GC_CCF, CONFIG_SYS_MB862xx_CCF); + /* Delay required */ + udelay(300); + /* Set Memory I/F Mode Register) */ + HOST_WR_REG (GC_MMR, CONFIG_SYS_MB862xx_MMR); + } #endif de_init (); @@ -385,6 +439,7 @@ void video_set_lut (unsigned int index, unsigned char r, L0PAL_WR_REG (index, (r << 16) | (g << 8) | (b)); } +#if defined(CONFIG_VIDEO_MB862xx_ACCEL) /* * Drawing engine Fill and BitBlt screen region */ @@ -395,7 +450,7 @@ void video_hw_rectfill (unsigned int bpp, unsigned int dst_x, GraphicDevice *dev = &mb862xx; de_wait_slots (3); - DE_WR_REG (0x0480, color); + DE_WR_REG (GC_FC, color); DE_WR_FIFO (0x09410000); DE_WR_FIFO ((dst_y << 16) | dst_x); DE_WR_FIFO ((dim_y << 16) | dim_x); @@ -426,3 +481,4 @@ void video_hw_bitblt (unsigned int bpp, unsigned int src_x, DE_WR_FIFO ((height << 16) | width); de_wait (); /* sync */ } +#endif