X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=drivers%2Fvideo%2Ftegra.c;h=f4bae9fc3694743878eeaf966bb626d29c7818a6;hb=d144f61ad3faa2104676791af58c2371729bef94;hp=57cb0074e277f97e35e40d78e889c31437cd156b;hpb=bcb879c0e37db1cf527ff408df93918f155012ea;p=u-boot diff --git a/drivers/video/tegra.c b/drivers/video/tegra.c index 57cb0074e2..f4bae9fc36 100644 --- a/drivers/video/tegra.c +++ b/drivers/video/tegra.c @@ -1,14 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Copyright (c) 2011 The Chromium OS Authors. - * SPDX-License-Identifier: GPL-2.0+ */ #include +#include #include -#include - +#include +#include +#include #include #include +#include #include #include @@ -19,281 +22,404 @@ DECLARE_GLOBAL_DATA_PTR; -/* These are the stages we go throuh in enabling the LCD */ -enum stage_t { - STAGE_START, - STAGE_PANEL_VDD, - STAGE_LVDS, - STAGE_BACKLIGHT_VDD, - STAGE_PWM, - STAGE_BACKLIGHT_EN, - STAGE_DONE, +/* Information about the display controller */ +struct tegra_lcd_priv { + int width; /* width in pixels */ + int height; /* height in pixels */ + enum video_log2_bpp log2_bpp; /* colour depth */ + struct display_timing timing; + struct udevice *panel; + struct disp_ctlr *disp; /* Display controller to use */ + fdt_addr_t frame_buffer; /* Address of frame buffer */ + unsigned pixel_clock; /* Pixel clock in Hz */ }; -static enum stage_t stage; /* Current stage we are at */ -static unsigned long timer_next; /* Time we can move onto next stage */ - -/* Our LCD config, set up in handle_stage() */ -static struct fdt_panel_config config; -struct fdt_disp_config *disp_config; /* Display controller config */ - enum { /* Maximum LCD size we support */ LCD_MAX_WIDTH = 1366, LCD_MAX_HEIGHT = 768, - LCD_MAX_LOG2_BPP = 4, /* 2^4 = 16 bpp */ + LCD_MAX_LOG2_BPP = VIDEO_BPP16, }; -vidinfo_t panel_info = { - /* Insert a value here so that we don't end up in the BSS */ - .vl_col = -1, -}; +static void update_window(struct dc_ctlr *dc, struct disp_ctl_win *win) +{ + unsigned h_dda, v_dda; + unsigned long val; -#ifndef CONFIG_OF_CONTROL -#error "You must enable CONFIG_OF_CONTROL to get Tegra LCD support" -#endif + val = readl(&dc->cmd.disp_win_header); + val |= WINDOW_A_SELECT; + writel(val, &dc->cmd.disp_win_header); -static void update_panel_size(struct fdt_disp_config *config) -{ - panel_info.vl_col = config->width; - panel_info.vl_row = config->height; - panel_info.vl_bpix = config->log2_bpp; -} + writel(win->fmt, &dc->win.color_depth); -/* - * Main init function called by lcd driver. - * Inits and then prints test pattern if required. - */ + clrsetbits_le32(&dc->win.byte_swap, BYTE_SWAP_MASK, + BYTE_SWAP_NOSWAP << BYTE_SWAP_SHIFT); -void lcd_ctrl_init(void *lcdbase) -{ - int type = DCACHE_OFF; - int size; - - assert(disp_config); - - /* Make sure that we can acommodate the selected LCD */ - assert(disp_config->width <= LCD_MAX_WIDTH); - assert(disp_config->height <= LCD_MAX_HEIGHT); - assert(disp_config->log2_bpp <= LCD_MAX_LOG2_BPP); - if (disp_config->width <= LCD_MAX_WIDTH - && disp_config->height <= LCD_MAX_HEIGHT - && disp_config->log2_bpp <= LCD_MAX_LOG2_BPP) - update_panel_size(disp_config); - size = lcd_get_size(&lcd_line_length); - - /* Set up the LCD caching as requested */ - if (config.cache_type & FDT_LCD_CACHE_WRITE_THROUGH) - type = DCACHE_WRITETHROUGH; - else if (config.cache_type & FDT_LCD_CACHE_WRITE_BACK) - type = DCACHE_WRITEBACK; - mmu_set_region_dcache_behaviour(disp_config->frame_buffer, size, type); + val = win->out_x << H_POSITION_SHIFT; + val |= win->out_y << V_POSITION_SHIFT; + writel(val, &dc->win.pos); - /* Enable flushing after LCD writes if requested */ - lcd_set_flush_dcache(config.cache_type & FDT_LCD_CACHE_FLUSH); + val = win->out_w << H_SIZE_SHIFT; + val |= win->out_h << V_SIZE_SHIFT; + writel(val, &dc->win.size); + + val = (win->w * win->bpp / 8) << H_PRESCALED_SIZE_SHIFT; + val |= win->h << V_PRESCALED_SIZE_SHIFT; + writel(val, &dc->win.prescaled_size); - debug("LCD frame buffer at %08X\n", disp_config->frame_buffer); + writel(0, &dc->win.h_initial_dda); + writel(0, &dc->win.v_initial_dda); + + h_dda = (win->w * 0x1000) / max(win->out_w - 1, 1U); + v_dda = (win->h * 0x1000) / max(win->out_h - 1, 1U); + + val = h_dda << H_DDA_INC_SHIFT; + val |= v_dda << V_DDA_INC_SHIFT; + writel(val, &dc->win.dda_increment); + + writel(win->stride, &dc->win.line_stride); + writel(0, &dc->win.buf_stride); + + val = WIN_ENABLE; + if (win->bpp < 24) + val |= COLOR_EXPAND; + writel(val, &dc->win.win_opt); + + writel((unsigned long)win->phys_addr, &dc->winbuf.start_addr); + writel(win->x, &dc->winbuf.addr_h_offset); + writel(win->y, &dc->winbuf.addr_v_offset); + + writel(0xff00, &dc->win.blend_nokey); + writel(0xff00, &dc->win.blend_1win); + + val = GENERAL_ACT_REQ | WIN_A_ACT_REQ; + val |= GENERAL_UPDATE | WIN_A_UPDATE; + writel(val, &dc->cmd.state_ctrl); } -ulong calc_fbsize(void) +static int update_display_mode(struct dc_disp_reg *disp, + struct tegra_lcd_priv *priv) { - return (panel_info.vl_col * panel_info.vl_row * - NBITS(panel_info.vl_bpix)) / 8; + struct display_timing *dt = &priv->timing; + unsigned long val; + unsigned long rate; + unsigned long div; + + writel(0x0, &disp->disp_timing_opt); + + writel(1 | 1 << 16, &disp->ref_to_sync); + writel(dt->hsync_len.typ | dt->vsync_len.typ << 16, &disp->sync_width); + writel(dt->hback_porch.typ | dt->vback_porch.typ << 16, + &disp->back_porch); + writel((dt->hfront_porch.typ - 1) | (dt->vfront_porch.typ - 1) << 16, + &disp->front_porch); + writel(dt->hactive.typ | (dt->vactive.typ << 16), &disp->disp_active); + + val = DE_SELECT_ACTIVE << DE_SELECT_SHIFT; + val |= DE_CONTROL_NORMAL << DE_CONTROL_SHIFT; + writel(val, &disp->data_enable_opt); + + val = DATA_FORMAT_DF1P1C << DATA_FORMAT_SHIFT; + val |= DATA_ALIGNMENT_MSB << DATA_ALIGNMENT_SHIFT; + val |= DATA_ORDER_RED_BLUE << DATA_ORDER_SHIFT; + writel(val, &disp->disp_interface_ctrl); + + /* + * The pixel clock divider is in 7.1 format (where the bottom bit + * represents 0.5). Here we calculate the divider needed to get from + * the display clock (typically 600MHz) to the pixel clock. We round + * up or down as requried. + */ + rate = clock_get_periph_rate(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL); + div = ((rate * 2 + priv->pixel_clock / 2) / priv->pixel_clock) - 2; + debug("Display clock %lu, divider %lu\n", rate, div); + + writel(0x00010001, &disp->shift_clk_opt); + + val = PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT; + val |= div << SHIFT_CLK_DIVIDER_SHIFT; + writel(val, &disp->disp_clk_ctrl); + + return 0; } -void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) +/* Start up the display and turn on power to PWMs */ +static void basic_init(struct dc_cmd_reg *cmd) { + u32 val; + + writel(0x00000100, &cmd->gen_incr_syncpt_ctrl); + writel(0x0000011a, &cmd->cont_syncpt_vsync); + writel(0x00000000, &cmd->int_type); + writel(0x00000000, &cmd->int_polarity); + writel(0x00000000, &cmd->int_mask); + writel(0x00000000, &cmd->int_enb); + + val = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE; + val |= PW3_ENABLE | PW4_ENABLE | PM0_ENABLE; + val |= PM1_ENABLE; + writel(val, &cmd->disp_pow_ctrl); + + val = readl(&cmd->disp_cmd); + val |= CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT; + writel(val, &cmd->disp_cmd); } -void tegra_lcd_early_init(const void *blob) +static void basic_init_timer(struct dc_disp_reg *disp) { - /* - * Go with the maximum size for now. We will fix this up after - * relocation. These values are only used for memory alocation. - */ - panel_info.vl_col = LCD_MAX_WIDTH; - panel_info.vl_row = LCD_MAX_HEIGHT; - panel_info.vl_bpix = LCD_MAX_LOG2_BPP; + writel(0x00000020, &disp->mem_high_pri); + writel(0x00000001, &disp->mem_high_pri_timer); } -/** - * Decode the panel information from the fdt. - * - * @param blob fdt blob - * @param config structure to store fdt config into - * @return 0 if ok, -ve on error - */ -static int fdt_decode_lcd(const void *blob, struct fdt_panel_config *config) +static const u32 rgb_enb_tab[PIN_REG_COUNT] = { + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; + +static const u32 rgb_polarity_tab[PIN_REG_COUNT] = { + 0x00000000, + 0x01000000, + 0x00000000, + 0x00000000, +}; + +static const u32 rgb_data_tab[PIN_REG_COUNT] = { + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; + +static const u32 rgb_sel_tab[PIN_OUTPUT_SEL_COUNT] = { + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00210222, + 0x00002200, + 0x00020000, +}; + +static void rgb_enable(struct dc_com_reg *com) { - int display_node; + int i; - disp_config = tegra_display_get_config(); - if (!disp_config) { - debug("%s: Display controller is not configured\n", __func__); - return -1; - } - display_node = disp_config->panel_node; - if (display_node < 0) { - debug("%s: No panel configuration available\n", __func__); - return -1; + for (i = 0; i < PIN_REG_COUNT; i++) { + writel(rgb_enb_tab[i], &com->pin_output_enb[i]); + writel(rgb_polarity_tab[i], &com->pin_output_polarity[i]); + writel(rgb_data_tab[i], &com->pin_output_data[i]); } - config->pwm_channel = pwm_request(blob, display_node, "nvidia,pwm"); - if (config->pwm_channel < 0) { - debug("%s: Unable to request PWM channel\n", __func__); + for (i = 0; i < PIN_OUTPUT_SEL_COUNT; i++) + writel(rgb_sel_tab[i], &com->pin_output_sel[i]); +} + +static int setup_window(struct disp_ctl_win *win, + struct tegra_lcd_priv *priv) +{ + win->x = 0; + win->y = 0; + win->w = priv->width; + win->h = priv->height; + win->out_x = 0; + win->out_y = 0; + win->out_w = priv->width; + win->out_h = priv->height; + win->phys_addr = priv->frame_buffer; + win->stride = priv->width * (1 << priv->log2_bpp) / 8; + debug("%s: depth = %d\n", __func__, priv->log2_bpp); + switch (priv->log2_bpp) { + case VIDEO_BPP32: + win->fmt = COLOR_DEPTH_R8G8B8A8; + win->bpp = 32; + break; + case VIDEO_BPP16: + win->fmt = COLOR_DEPTH_B5G6R5; + win->bpp = 16; + break; + + default: + debug("Unsupported LCD bit depth"); return -1; } - config->cache_type = fdtdec_get_int(blob, display_node, - "nvidia,cache-type", - FDT_LCD_CACHE_WRITE_BACK_FLUSH); - - /* These GPIOs are all optional */ - fdtdec_decode_gpio(blob, display_node, "nvidia,backlight-enable-gpios", - &config->backlight_en); - fdtdec_decode_gpio(blob, display_node, "nvidia,lvds-shutdown-gpios", - &config->lvds_shutdown); - fdtdec_decode_gpio(blob, display_node, "nvidia,backlight-vdd-gpios", - &config->backlight_vdd); - fdtdec_decode_gpio(blob, display_node, "nvidia,panel-vdd-gpios", - &config->panel_vdd); - - return fdtdec_get_int_array(blob, display_node, "nvidia,panel-timings", - config->panel_timings, FDT_LCD_TIMINGS); + return 0; } /** - * Handle the next stage of device init + * Register a new display based on device tree configuration. + * + * The frame buffer can be positioned by U-Boot or overridden by the fdt. + * You should pass in the U-Boot address here, and check the contents of + * struct tegra_lcd_priv to see what was actually chosen. + * + * @param blob Device tree blob + * @param priv Driver's private data + * @param default_lcd_base Default address of LCD frame buffer + * @return 0 if ok, -1 on error (unsupported bits per pixel) */ -static int handle_stage(const void *blob) +static int tegra_display_probe(const void *blob, struct tegra_lcd_priv *priv, + void *default_lcd_base) { - debug("%s: stage %d\n", __func__, stage); - - /* do the things for this stage */ - switch (stage) { - case STAGE_START: - /* Initialize the Tegra display controller */ - if (tegra_display_probe(gd->fdt_blob, (void *)gd->fb_base)) { - printf("%s: Failed to probe display driver\n", - __func__); - return -1; - } - - /* get panel details */ - if (fdt_decode_lcd(blob, &config)) { - printf("No valid LCD information in device tree\n"); - return -1; - } - - /* - * It is possible that the FDT has requested that the LCD be - * disabled. We currently don't support this. It would require - * changes to U-Boot LCD subsystem to have LCD support - * compiled in but not used. An easier option might be to - * still have a frame buffer, but leave the backlight off and - * remove all mention of lcd in the stdout environment - * variable. - */ - - funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT); - - fdtdec_setup_gpio(&config.panel_vdd); - fdtdec_setup_gpio(&config.lvds_shutdown); - fdtdec_setup_gpio(&config.backlight_vdd); - fdtdec_setup_gpio(&config.backlight_en); - - /* - * TODO: If fdt includes output flag we can omit this code - * since fdtdec_setup_gpio will do it for us. - */ - if (fdt_gpio_isvalid(&config.panel_vdd)) - gpio_direction_output(config.panel_vdd.gpio, 0); - if (fdt_gpio_isvalid(&config.lvds_shutdown)) - gpio_direction_output(config.lvds_shutdown.gpio, 0); - if (fdt_gpio_isvalid(&config.backlight_vdd)) - gpio_direction_output(config.backlight_vdd.gpio, 0); - if (fdt_gpio_isvalid(&config.backlight_en)) - gpio_direction_output(config.backlight_en.gpio, 0); - break; - case STAGE_PANEL_VDD: - if (fdt_gpio_isvalid(&config.panel_vdd)) - gpio_direction_output(config.panel_vdd.gpio, 1); - break; - case STAGE_LVDS: - if (fdt_gpio_isvalid(&config.lvds_shutdown)) - gpio_set_value(config.lvds_shutdown.gpio, 1); - break; - case STAGE_BACKLIGHT_VDD: - if (fdt_gpio_isvalid(&config.backlight_vdd)) - gpio_set_value(config.backlight_vdd.gpio, 1); - break; - case STAGE_PWM: - /* Enable PWM at 15/16 high, 32768 Hz with divider 1 */ - pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_PWM); - pinmux_tristate_disable(PMUX_PINGRP_GPU); + struct disp_ctl_win window; + struct dc_ctlr *dc; - pwm_enable(config.pwm_channel, 32768, 0xdf, 1); - break; - case STAGE_BACKLIGHT_EN: - if (fdt_gpio_isvalid(&config.backlight_en)) - gpio_set_value(config.backlight_en.gpio, 1); - break; - case STAGE_DONE: - break; - } + priv->frame_buffer = (u32)default_lcd_base; + + dc = (struct dc_ctlr *)priv->disp; - /* set up timer for next stage */ - timer_next = timer_get_us(); - if (stage < FDT_LCD_TIMINGS) - timer_next += config.panel_timings[stage] * 1000; + /* + * A header file for clock constants was NAKed upstream. + * TODO: Put this into the FDT and fdt_lcd struct when we have clock + * support there + */ + clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH, + 144 * 1000000); + clock_start_periph_pll(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL, + 600 * 1000000); + basic_init(&dc->cmd); + basic_init_timer(&dc->disp); + rgb_enable(&dc->com); + + if (priv->pixel_clock) + update_display_mode(&dc->disp, priv); + + if (setup_window(&window, priv)) + return -1; + + update_window(dc, &window); - /* move to next stage */ - stage++; return 0; } -int tegra_lcd_check_next_stage(const void *blob, int wait) +static int tegra_lcd_probe(struct udevice *dev) { - if (stage == STAGE_DONE) - return 0; - - do { - /* wait if we need to */ - debug("%s: stage %d\n", __func__, stage); - if (stage != STAGE_START) { - int delay = timer_next - timer_get_us(); - - if (delay > 0) { - if (wait) - udelay(delay); - else - return 0; - } - } - - if (handle_stage(blob)) - return -1; - } while (wait && stage != STAGE_DONE); - if (stage == STAGE_DONE) - debug("%s: LCD init complete\n", __func__); + struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); + struct video_priv *uc_priv = dev_get_uclass_priv(dev); + struct tegra_lcd_priv *priv = dev_get_priv(dev); + const void *blob = gd->fdt_blob; + int ret; + + /* Initialize the Tegra display controller */ + funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT); + if (tegra_display_probe(blob, priv, (void *)plat->base)) { + printf("%s: Failed to probe display driver\n", __func__); + return -1; + } + + pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_PWM); + pinmux_tristate_disable(PMUX_PINGRP_GPU); + + ret = panel_enable_backlight(priv->panel); + if (ret) { + debug("%s: Cannot enable backlight, ret=%d\n", __func__, ret); + return ret; + } + + mmu_set_region_dcache_behaviour(priv->frame_buffer, plat->size, + DCACHE_WRITETHROUGH); + + /* Enable flushing after LCD writes if requested */ + video_set_flush_dcache(dev, true); + + uc_priv->xsize = priv->width; + uc_priv->ysize = priv->height; + uc_priv->bpix = priv->log2_bpp; + debug("LCD frame buffer at %pa, size %x\n", &priv->frame_buffer, + plat->size); return 0; } -void lcd_enable(void) +static int tegra_lcd_ofdata_to_platdata(struct udevice *dev) { + struct tegra_lcd_priv *priv = dev_get_priv(dev); + const void *blob = gd->fdt_blob; + struct display_timing *timing; + int node = dev_of_offset(dev); + int panel_node; + int rgb; + int ret; + + priv->disp = (struct disp_ctlr *)devfdt_get_addr(dev); + if (!priv->disp) { + debug("%s: No display controller address\n", __func__); + return -EINVAL; + } + + rgb = fdt_subnode_offset(blob, node, "rgb"); + if (rgb < 0) { + debug("%s: Cannot find rgb subnode for '%s' (ret=%d)\n", + __func__, dev->name, rgb); + return -EINVAL; + } + + ret = fdtdec_decode_display_timing(blob, rgb, 0, &priv->timing); + if (ret) { + debug("%s: Cannot read display timing for '%s' (ret=%d)\n", + __func__, dev->name, ret); + return -EINVAL; + } + timing = &priv->timing; + priv->width = timing->hactive.typ; + priv->height = timing->vactive.typ; + priv->pixel_clock = timing->pixelclock.typ; + priv->log2_bpp = VIDEO_BPP16; + /* - * Backlight and power init will be done separately in - * tegra_lcd_check_next_stage(), which should be called in - * board_late_init(). - * - * U-Boot code supports only colour depth, selected at compile time. - * The device tree setting should match this. Otherwise the display - * will not look right, and U-Boot may crash. + * Sadly the panel phandle is in an rgb subnode so we cannot use + * uclass_get_device_by_phandle(). */ - if (disp_config->log2_bpp != LCD_BPP) { - printf("%s: Error: LCD depth configured in FDT (%d = %dbpp)" - " must match setting of LCD_BPP (%d)\n", __func__, - disp_config->log2_bpp, disp_config->bpp, LCD_BPP); + panel_node = fdtdec_lookup_phandle(blob, rgb, "nvidia,panel"); + if (panel_node < 0) { + debug("%s: Cannot find panel information\n", __func__); + return -EINVAL; + } + ret = uclass_get_device_by_of_offset(UCLASS_PANEL, panel_node, + &priv->panel); + if (ret) { + debug("%s: Cannot find panel for '%s' (ret=%d)\n", __func__, + dev->name, ret); + return ret; } + + return 0; } + +static int tegra_lcd_bind(struct udevice *dev) +{ + struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); + const void *blob = gd->fdt_blob; + int node = dev_of_offset(dev); + int rgb; + + rgb = fdt_subnode_offset(blob, node, "rgb"); + if ((rgb < 0) || !fdtdec_get_is_enabled(blob, rgb)) + return -ENODEV; + + plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT * + (1 << LCD_MAX_LOG2_BPP) / 8; + + return 0; +} + +static const struct video_ops tegra_lcd_ops = { +}; + +static const struct udevice_id tegra_lcd_ids[] = { + { .compatible = "nvidia,tegra20-dc" }, + { } +}; + +U_BOOT_DRIVER(tegra_lcd) = { + .name = "tegra_lcd", + .id = UCLASS_VIDEO, + .of_match = tegra_lcd_ids, + .ops = &tegra_lcd_ops, + .bind = tegra_lcd_bind, + .probe = tegra_lcd_probe, + .ofdata_to_platdata = tegra_lcd_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct tegra_lcd_priv), +};