X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2F_6522.h;h=d6eedcf751e49c6a49ac12c878068334c7080d2e;hb=df80d071e8eeb799bd1d8ec55acd1ee92714c752;hp=d5dbc5f75d448ed4474cd8b74dfb5d0b5298db73;hpb=3d8aa8c7d85f6c6eff6360f7b9447c583bcbf8cc;p=cc65

diff --git a/include/_6522.h b/include/_6522.h
index d5dbc5f75..d6eedcf75 100644
--- a/include/_6522.h
+++ b/include/_6522.h
@@ -2,7 +2,7 @@
 /*                                                                           */
 /*                                  _6522.h                                  */
 /*                                                                           */
-/*		  Internal include file, do not use directly                 */
+/*                Internal include file, do not use directly                 */
 /*                                                                           */
 /*                                                                           */
 /*                                                                           */
@@ -36,27 +36,27 @@
 
 
 /* Define a structure with the 6522 register offsets.
- * NOTE: The timer registers are not declared as 16 bit registers, because
- * the order in which the two 8 bit halves are written is important, and
- * the compiler doesn't guarantee any order when writing 16 bit values.
- */
+** NOTE: The timer registers are not declared as 16 bit registers, because
+** the order in which the two 8 bit halves are written is important, and
+** the compiler doesn't guarantee any order when writing 16 bit values.
+*/
 struct __6522 {
-    unsigned char	prb;		/* Port register B */
-    unsigned char	pra;		/* Port register A */
-    unsigned char	ddrb;		/* Data direction register B */
-    unsigned char	ddra;		/* Data direction register A */
-    unsigned char	t1_lo;		/* Timer 1, low byte */
-    unsigned char	t1_hi;		/* Timer 1, high byte */
-    unsigned char	t1l_lo;		/* Timer 1 latch, low byte */
-    unsigned char	t1l_hi;		/* Timer 1 latch, high byte */
-    unsigned char	t2_lo;		/* Timer 2, low byte */
-    unsigned char	t2_hi;		/* Timer 2, high byte */
-    unsigned char	sr;		/* Shift register */
-    unsigned char	acr;		/* Auxiliary control register */
-    unsigned char	pcr;		/* Peripheral control register */
-    unsigned char	ifr;		/* Interrupt flag register */
-    unsigned char	ier;		/* Interrupt enable register */
-    unsigned char	pra2;		/* Port register A w/o handshake */
+    unsigned char       prb;            /* Port register B */
+    unsigned char       pra;            /* Port register A */
+    unsigned char       ddrb;           /* Data direction register B */
+    unsigned char       ddra;           /* Data direction register A */
+    unsigned char       t1_lo;          /* Timer 1, low byte */
+    unsigned char       t1_hi;          /* Timer 1, high byte */
+    unsigned char       t1l_lo;         /* Timer 1 latch, low byte */
+    unsigned char       t1l_hi;         /* Timer 1 latch, high byte */
+    unsigned char       t2_lo;          /* Timer 2, low byte */
+    unsigned char       t2_hi;          /* Timer 2, high byte */
+    unsigned char       sr;             /* Shift register */
+    unsigned char       acr;            /* Auxiliary control register */
+    unsigned char       pcr;            /* Peripheral control register */
+    unsigned char       ifr;            /* Interrupt flag register */
+    unsigned char       ier;            /* Interrupt enable register */
+    unsigned char       pra2;           /* Port register A w/o handshake */
 };