X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fasm-arm%2Farch-at91%2Fat91sam9_sdramc.h;h=c3da3a6a35bbc14571b4a2c6e77c288bdb68d7e6;hb=5d8e359c38d3ab80015e47d0cab792efe75cacf9;hp=5af2b54b123847306a13f3f448a86f870b55f43a;hpb=425de62d40f84524b90e776b141b060cd438a9fe;p=u-boot

diff --git a/include/asm-arm/arch-at91/at91sam9_sdramc.h b/include/asm-arm/arch-at91/at91sam9_sdramc.h
index 5af2b54b12..c3da3a6a35 100644
--- a/include/asm-arm/arch-at91/at91sam9_sdramc.h
+++ b/include/asm-arm/arch-at91/at91sam9_sdramc.h
@@ -17,6 +17,19 @@
 #ifndef AT91SAM9_SDRAMC_H
 #define AT91SAM9_SDRAMC_H
 
+#ifdef __ASSEMBLY__
+
+#ifndef AT91_SDRAMC_BASE
+#define AT91_SDRAMC_BASE	AT91_SDRAMC0_BASE
+#endif
+
+#define AT91_ASM_SDRAMC_MR	AT91_SDRAMC_BASE
+#define AT91_ASM_SDRAMC_TR	(AT91_SDRAMC_BASE + 0x04)
+#define AT91_ASM_SDRAMC_CR	(AT91_SDRAMC_BASE + 0x08)
+#define AT91_ASM_SDRAMC_MDR	(AT91_SDRAMC_BASE + 0x24)
+
+#endif
+
 /* SDRAM Controller (SDRAMC) registers */
 #define AT91_SDRAMC_MR		(AT91_SDRAMC + 0x00)	/* SDRAM Controller Mode Register */
 #define		AT91_SDRAMC_MODE	(0xf << 0)		/* Command Mode */