X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fasm-blackfin%2Fcpu%2Fdef_LPBlackfin.h;h=9ac78c836a606accbf68c215bf040fe1e6593fad;hb=007d67da94db86989c3d0ad0a9728391b7eed02b;hp=11a6504391ee6ae5a3bc7f6afaf7009e38e6406f;hpb=6cb142fa3b732a2cea257ca39ef4a7dbe81a32e1;p=u-boot

diff --git a/include/asm-blackfin/cpu/def_LPBlackfin.h b/include/asm-blackfin/cpu/def_LPBlackfin.h
index 11a6504391..9ac78c836a 100644
--- a/include/asm-blackfin/cpu/def_LPBlackfin.h
+++ b/include/asm-blackfin/cpu/def_LPBlackfin.h
@@ -21,7 +21,7 @@
 #ifndef _DEF_LPBLACKFIN_H
 #define _DEF_LPBLACKFIN_H
 
-/* 
+/*
  * #if !defined(__ADSPLPBLACKFIN__)
  * #warning def_LPBlackfin.h should only be included for 532 compatible chips.
  * #endif
@@ -344,9 +344,9 @@
 /* ** Masks */
 #define ENDM			0x00000001	/* (doesn't really exist) Enable Data Memory L1 */
 #define ENDCPLB			0x00000002	/* Enable DCPLB */
-#define ASRAM_BSRAM		0x00000000	
+#define ASRAM_BSRAM		0x00000000
 #define ACACHE_BSRAM		0x00000008
-#define ACACHE_BCACHE		0x0000000C  
+#define ACACHE_BCACHE		0x0000000C
 #define DCBS			0x00000010	/*  L1 Data Cache Bank Select */
 #define PORT_PREF0		0x00001000	/* DAG0 Port Preference */
 #define PORT_PREF1		0x00002000	/* DAG1 Port Preference */