X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fasm-ppc%2Fimmap_85xx.h;h=7a4345a74085e9d0c034930c6d1873fff904aa2f;hb=92c427b18982167064de454ae5248ec466998919;hp=542a7d57125a5ba0b6eb9545ea80fa3e92f5a8df;hpb=03f5c55021c2d6297e66cc11bfea75f149a5d71c;p=u-boot diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 542a7d5712..7a4345a740 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -9,9 +9,9 @@ #ifndef __IMMAP_85xx__ #define __IMMAP_85xx__ - -/* Local-Access Registers and ECM Registers(0x0000-0x2000) */ - +/* + * Local-Access Registers and ECM Registers(0x0000-0x2000) + */ typedef struct ccsr_local_ecm { uint ccsrbar; /* 0x0 - Control Configuration Status Registers Base Address Register */ char res1[4]; @@ -65,9 +65,9 @@ typedef struct ccsr_local_ecm { char res24[492]; } ccsr_local_ecm_t; - -/* DDR memory controller registers(0x2000-0x3000) */ - +/* + * DDR memory controller registers(0x2000-0x3000) + */ typedef struct ccsr_ddr { uint cs0_bnds; /* 0x2000 - DDR Chip Select 0 Memory Bounds */ char res1[4]; @@ -81,21 +81,27 @@ typedef struct ccsr_ddr { uint cs1_config; /* 0x2084 - DDR Chip Select Configuration */ uint cs2_config; /* 0x2088 - DDR Chip Select Configuration */ uint cs3_config; /* 0x208c - DDR Chip Select Configuration */ - char res5[120]; + char res5[112]; + uint ext_refrec; /* 0x2100 - DDR SDRAM Extended Refresh Recovery */ + uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */ uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */ uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */ uint sdram_cfg; /* 0x2110 - DDR SDRAM Control Configuration */ - char res6[4]; + uint sdram_cfg_2; /* 0x2114 - DDR SDRAM Control Configuration 2 */ uint sdram_mode; /* 0x2118 - DDR SDRAM Mode Configuration */ - char res7[8]; + uint sdram_mode_2; /* 0x211c - DDR SDRAM Mode Configuration 2*/ + uint sdram_md_cntl; /* 0x2120 - DDR SDRAM Mode Control */ uint sdram_interval; /* 0x2124 - DDR SDRAM Interval Configuration */ -#ifdef MPC85xx_DDR_SDRAM_CLK_CNTL - char res7_5[8]; + uint sdram_data_init; /* 0x2128 - DDR SDRAM Data initialization */ + char res6[4]; uint sdram_clk_cntl; /* 0x2130 - DDR SDRAM Clock Control */ - char res8[3276]; -#else - char res8[3288]; -#endif + char res7[20]; + uint init_address; /* 0x2148 - DDR training initialization address */ + uint init_ext_address; /* 0x214C - DDR training initialization extended address */ + char res8_1[2728]; + uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */ + uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */ + char res8_2[512]; uint data_err_inject_hi; /* 0x2e00 - DDR Memory Data Path Error Injection Mask High */ uint data_err_inject_lo; /* 0x2e04 - DDR Memory Data Path Error Injection Mask Low */ uint ecc_err_inject; /* 0x2e08 - DDR Memory Data Path Error Injection Mask ECC */ @@ -119,9 +125,9 @@ typedef struct ccsr_ddr { char res12[240]; } ccsr_ddr_t; - -/* I2C Registers(0x3000-0x4000) */ - +/* + * I2C Registers(0x3000-0x4000) + */ typedef struct ccsr_i2c { u_char i2cadr; /* 0x3000 - I2C Address Register */ #define MPC85xx_I2CADR_MASK 0xFE @@ -158,6 +164,7 @@ typedef struct ccsr_i2c { #if defined(CONFIG_MPC8540) \ || defined(CONFIG_MPC8541) \ + || defined(CONFIG_MPC8548) \ || defined(CONFIG_MPC8555) /* DUART Registers(0x4000-0x5000) */ typedef struct ccsr_duart { @@ -237,10 +244,9 @@ typedef struct ccsr_lbc { char res8[12072]; } ccsr_lbc_t; - -/* PCI Registers(0x8000-0x9000) */ -/* Omitting Reserved(0x9000-0x2_0000) */ - +/* + * PCI Registers(0x8000-0x9000) + */ typedef struct ccsr_pcix { uint cfg_addr; /* 0x8000 - PCIX Configuration Address Register */ uint cfg_data; /* 0x8004 - PCIX Configuration Data Register */ @@ -302,12 +308,30 @@ typedef struct ccsr_pcix { uint peextaddrcr; /* 0x8e14 - PCIX Error Extended Address Capture Register */ uint pedlcr; /* 0x8e18 - PCIX Error Data Low Capture Register */ uint pedhcr; /* 0x8e1c - PCIX Error Error Data High Capture Register */ - char res11[94688]; + uint gas_timr; /* 0x8e20 - PCIX Gasket Timer Register */ + char res11[476]; } ccsr_pcix_t; +#define PCIX_COMMAND 0x62 +#define POWAR_EN 0x80000000 +#define POWAR_IO_READ 0x00080000 +#define POWAR_MEM_READ 0x00040000 +#define POWAR_IO_WRITE 0x00008000 +#define POWAR_MEM_WRITE 0x00004000 +#define POWAR_MEM_512M 0x0000001c +#define POWAR_IO_1M 0x00000013 -/* L2 Cache Registers(0x2_0000-0x2_1000) */ +#define PIWAR_EN 0x80000000 +#define PIWAR_PF 0x20000000 +#define PIWAR_LOCAL 0x00f00000 +#define PIWAR_READ_SNOOP 0x00050000 +#define PIWAR_WRITE_SNOOP 0x00005000 +#define PIWAR_MEM_2G 0x0000001e + +/* + * L2 Cache Registers(0x2_0000-0x2_1000) + */ typedef struct ccsr_l2cache { uint l2ctl; /* 0x20000 - L2 configuration register 0 */ char res1[12]; @@ -349,9 +373,9 @@ typedef struct ccsr_l2cache { char res15[420]; } ccsr_l2cache_t; - -/* DMA Registers(0x2_1000-0x2_2000) */ - +/* + * DMA Registers(0x2_1000-0x2_2000) + */ typedef struct ccsr_dma { char res1[256]; uint mr0; /* 0x21100 - DMA 0 Mode Register */ @@ -430,7 +454,9 @@ typedef struct ccsr_dma { char res22[11516]; } ccsr_dma_t; -/* tsec1 tsec2: 24000-26000 */ +/* + * tsec1 tsec2: 24000-26000 + */ typedef struct ccsr_tsec { char res1[16]; uint ievent; /* 0x24010 - Interrupt Event Register */ @@ -717,8 +743,9 @@ typedef struct ccsr_tsec { char res74[1024]; } ccsr_tsec_t; -/* PIC Registers(0x2_6000-0x4_0000-0x8_0000) */ - +/* + * PIC Registers(0x2_6000-0x4_0000-0x8_0000) + */ typedef struct ccsr_pic { char res0[106496]; /* 0x26000-0x40000 */ char res1[64]; @@ -741,6 +768,8 @@ typedef struct ccsr_pic { uint frr; /* 0x41000 - Feature Reporting Register */ char res10[28]; uint gcr; /* 0x41020 - Global Configuration Register */ +#define MPC85xx_PICGCR_RST 0x80000000 +#define MPC85xx_PICGCR_M 0x20000000 char res11[92]; uint vir; /* 0x41080 - Vendor Identification Register */ char res12[12]; @@ -1022,17 +1051,18 @@ typedef struct ccsr_pic { char res150[130892]; } ccsr_pic_t; -/* CPM Block(0x8_0000-0xc_0000) */ -#if defined(CONFIG_MPC8540) \ - || defined(CONFIG_MPC8541) \ - || defined(CONFIG_MPC8555) +/* + * CPM Block(0x8_0000-0xc_0000) + */ +#ifndef CONFIG_CPM2 typedef struct ccsr_cpm { char res[262144]; } ccsr_cpm_t; #else -/* 0x8000-0x8ffff:DPARM */ - -/* 0x9000-0x90bff: General SIU */ +/* + * 0x8000-0x8ffff:DPARM + * 0x9000-0x90bff: General SIU + */ typedef struct ccsr_cpm_siu { char res1[80]; uint smaer; @@ -1323,7 +1353,6 @@ typedef struct ccsr_cpm { char res1[16*1024]; u_char im_dpram2[16*1024]; char res2[16*1024]; - ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */ ccsr_cpm_intctl_t im_cpm_intctl; /* Interrupt Controller */ ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */ @@ -1348,8 +1377,10 @@ typedef struct ccsr_cpm { ccsr_cpm_iram_t im_cpm_iram; } ccsr_cpm_t; #endif -/* RapidIO Registers(0xc_0000-0xe_0000) */ +/* + * RapidIO Registers(0xc_0000-0xe_0000) + */ typedef struct ccsr_rio { uint didcar; /* 0xc0000 - Device Identity Capability Register */ uint dicar; /* 0xc0004 - Device Information Capability Register */ @@ -1515,7 +1546,9 @@ typedef struct ccsr_rio { char res58[60176]; } ccsr_rio_t; -/* Global Utilities Register Block(0xe_0000-0xf_ffff) */ +/* + * Global Utilities Register Block(0xe_0000-0xf_ffff) + */ typedef struct ccsr_gur { uint porpllsr; /* 0xe0000 - POR PLL ratio status register */ uint porbmsr; /* 0xe0004 - POR boot mode status register */ @@ -1547,9 +1580,17 @@ typedef struct ccsr_gur { uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */ char res12[12]; uint lbcdllcr; /* 0xe0e20 - LBC DLL control register */ - char res13[61915]; + char res13[248]; + uint lbiuiplldcr0; /* 0xe0f1c -- LBIU PLL Debug Reg 0 */ + uint lbiuiplldcr1; /* 0xe0f20 -- LBIU PLL Debug Reg 1 */ + uint ddrioovcr; /* 0xe0f24 - DDR IO Override Control */ + uint res14; /* 0xe0f28 */ + uint tsec34ioovcr; /* 0xe0f2c - eTSEC 3/4 IO override control */ + char res15[61651]; } ccsr_gur_t; +#define PORDEVSR_PCI (0x00800000) /* PCI Mode */ + typedef struct immap { ccsr_local_ecm_t im_local_ecm; ccsr_ddr_t im_ddr; @@ -1557,6 +1598,8 @@ typedef struct immap { ccsr_duart_t im_duart; ccsr_lbc_t im_lbc; ccsr_pcix_t im_pcix; + ccsr_pcix_t im_pcix2; + char reserved[90112]; ccsr_l2cache_t im_l2cache; ccsr_dma_t im_dma; ccsr_tsec_t im_tsec1;