X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fasm-ppc%2Fimmap_85xx.h;h=d3c6b86d2b179b3f1f1d9b4abc6241bdf03e8e97;hb=712ac6a1a6909a58d6549fb220cc921a7e9f9979;hp=3506aec5ec5e5ebef5d7f162ac2d164c6ec6d649;hpb=38b189fe749824ea9b1c5422865e78b4b7eb2494;p=u-boot diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 3506aec5ec..d3c6b86d2b 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -13,6 +13,7 @@ #include #include +#include /* * Local-Access Registers and ECM Registers(0x0000-0x2000) @@ -57,7 +58,23 @@ typedef struct ccsr_local_ecm { uint lawbar7; /* 0xce8 - Local Access Window 7 Base Address Register */ char res19[4]; uint lawar7; /* 0xcf0 - Local Access Window 7 Attributes Register */ - char res20[780]; // XXX: LAW 8, LAW9 for 8572 + char res19_8a[20]; + uint lawbar8; /* 0xd08 - Local Access Window 8 Base Address Register */ + char res19_8b[4]; + uint lawar8; /* 0xd10 - Local Access Window 8 Attributes Register */ + char res19_9a[20]; + uint lawbar9; /* 0xd28 - Local Access Window 9 Base Address Register */ + char res19_9b[4]; + uint lawar9; /* 0xd30 - Local Access Window 9 Attributes Register */ + char res19_10a[20]; + uint lawbar10; /* 0xd48 - Local Access Window 10 Base Address Register */ + char res19_10b[4]; + uint lawar10; /* 0xd50 - Local Access Window 10 Attributes Register */ + char res19_11a[20]; + uint lawbar11; /* 0xd68 - Local Access Window 11 Base Address Register */ + char res19_11b[4]; + uint lawar11; /* 0xd70 - Local Access Window 11 Attributes Register */ + char res20[652]; uint eebacr; /* 0x1000 - ECM CCB Address Configuration Register */ char res21[12]; uint eebpcr; /* 0x1010 - ECM CCB Port Configuration Register */ @@ -92,7 +109,7 @@ typedef struct ccsr_ddr { uint cs2_config_2; /* 0x20c8 - DDR Chip Select Configuration 2 */ uint cs3_config_2; /* 0x20cc - DDR Chip Select Configuration 2 */ char res5[48]; - uint ext_refrec; /* 0x2100 - DDR SDRAM Extended Refresh Recovery */ + uint timing_cfg_3; /* 0x2100 - DDR SDRAM Timing Configuration Register 3 */ uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */ uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */ uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */ @@ -106,8 +123,8 @@ typedef struct ccsr_ddr { char res6[4]; uint sdram_clk_cntl; /* 0x2130 - DDR SDRAM Clock Control */ char res7[20]; - uint init_address; /* 0x2148 - DDR training initialization address */ - uint init_ext_address; /* 0x214C - DDR training initialization extended address */ + uint init_addr; /* 0x2148 - DDR training initialization address */ + uint init_ext_addr; /* 0x214C - DDR training initialization extended address */ char res8_1[16]; uint timing_cfg_4; /* 0x2160 - DDR SDRAM Timing Configuration Register 4 */ uint timing_cfg_5; /* 0x2164 - DDR SDRAM Timing Configuration Register 5 */ @@ -118,7 +135,12 @@ typedef struct ccsr_ddr { uint ddr_sr_cntr; /* 0x217C - DDR self refresh counter */ uint ddr_sdram_rcw_1; /* 0x2180 - DDR Register Control Words 1 */ uint ddr_sdram_rcw_2; /* 0x2184 - DDR Register Control Words 2 */ - char res8_1b[2672]; + char res8_1b[2456]; + uint ddr_dsr1; /* 0x2B20 - DDR Debug Status Register 1 */ + uint ddr_dsr2; /* 0x2B24 - DDR Debug Status Register 2 */ + uint ddr_cdr1; /* 0x2B28 - DDR Control Driver Register 1 */ + uint ddr_cdr2; /* 0x2B2C - DDR Control Driver Register 2 */ + char res8_1c[200]; uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */ uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */ char res8_2[512]; @@ -235,6 +257,21 @@ typedef struct ccsr_lbc { char res8[3880]; } ccsr_lbc_t; +/* + * eSPI Registers(0x7000-0x8000) + */ +typedef struct ccsr_espi { + uint mode; /* 0x00 - eSPI mode register */ + uint event; /* 0x04 - eSPI event register */ + uint mask; /* 0x08 - eSPI mask register */ + uint com; /* 0x0c - eSPI command register */ + uint tx; /* 0x10 - eSPI transmit FIFO access register */ + uint rx; /* 0x14 - eSPI receive FIFO access register */ + char res1[8]; /* reserved */ + uint csmode[4]; /* 0x20 - 0x2c: sSPI CS0/1/2/3 mode register */ + char res2[4048]; /* fill up to 0x1000 */ +} ccsr_espi_t; + /* * PCI Registers(0x8000-0x9000) */ @@ -1054,7 +1091,7 @@ typedef struct ccsr_cpm { * 0x9000-0x90bff: General SIU */ typedef struct ccsr_cpm_siu { - char res1[80]; + char res1[80]; uint smaer; uint smser; uint smevr; @@ -1143,9 +1180,9 @@ typedef struct ccsr_cpm_timer { /* 0x91018-0x912ff: SDMA */ typedef struct ccsr_cpm_sdma { uchar sdsr; - char res1[3]; - uchar sdmr; - char res2[739]; + char res1[3]; + uchar sdmr; + char res2[739]; } ccsr_cpm_sdma_t; /* 0x91300-0x9131f: FCC1 */ @@ -1228,7 +1265,7 @@ typedef struct ccsr_cpm_fcc3_ext { /* 0x91400-0x915ef: TC layers */ typedef struct ccsr_cpm_tmp1 { - char res[496]; + char res[496]; } ccsr_cpm_tmp1_t; /* 0x915f0-0x9185f: BRGs:5,6,7,8 */ @@ -1296,7 +1333,7 @@ typedef struct ccsr_cpm_scc { /* 0x91a80-0x91a9f */ typedef struct ccsr_cpm_tmp2 { - char res[32]; + char res[32]; } ccsr_cpm_tmp2_t; /* 0x91aa0-0x91aff: SPI */ @@ -1338,16 +1375,16 @@ typedef struct ccsr_cpm { /* Some references are into the unique and known dpram spaces, * others are from the generic base. */ -#define im_dprambase im_dpram1 - u_char im_dpram1[16*1024]; - char res1[16*1024]; - u_char im_dpram2[16*1024]; - char res2[16*1024]; - ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */ - ccsr_cpm_intctl_t im_cpm_intctl; /* Interrupt Controller */ - ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */ - ccsr_cpm_timer_t im_cpm_timer; /* CPM timers */ - ccsr_cpm_sdma_t im_cpm_sdma; /* SDMA control/status */ +#define im_dprambase im_dpram1 + u_char im_dpram1[16*1024]; + char res1[16*1024]; + u_char im_dpram2[16*1024]; + char res2[16*1024]; + ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */ + ccsr_cpm_intctl_t im_cpm_intctl; /* Interrupt Controller */ + ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */ + ccsr_cpm_timer_t im_cpm_timer; /* CPM timers */ + ccsr_cpm_sdma_t im_cpm_sdma; /* SDMA control/status */ ccsr_cpm_fcc1_t im_cpm_fcc1; ccsr_cpm_fcc2_t im_cpm_fcc2; ccsr_cpm_fcc3_t im_cpm_fcc3; @@ -1552,34 +1589,60 @@ typedef struct par_io { */ typedef struct ccsr_gur { uint porpllsr; /* 0xe0000 - POR PLL ratio status register */ +#ifdef CONFIG_MPC8536 +#define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000 +#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25 +#else +#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00 +#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9 +#endif uint porbmsr; /* 0xe0004 - POR boot mode status register */ -#define MPC85xx_PORBMSR_HA 0x00070000 +#define MPC85xx_PORBMSR_HA 0x00070000 uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */ uint pordevsr; /* 0xe000c - POR I/O device status regsiter */ #define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000 #define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000 #define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000 #define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000 -#define MPC85xx_PORDEVSR_IO_SEL 0x00380000 -#define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000 -#define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000 -#define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000 -#define MPC85xx_PORDEVSR_PCI1_SPD 0x00008000 -#define MPC85xx_PORDEVSR_PCI2_SPD 0x00004000 +#define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000 +#define MPC85xx_PORDEVSR_PCI1 0x00800000 +#define MPC85xx_PORDEVSR_IO_SEL 0x00780000 +#define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000 +#define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000 +#define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000 +#define MPC85xx_PORDEVSR_PCI1_SPD 0x00008000 +#define MPC85xx_PORDEVSR_PCI2_SPD 0x00004000 #define MPC85xx_PORDEVSR_DRAM_RTYPE 0x00000060 -#define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008 +#define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008 #define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007 uint pordbgmsr; /* 0xe0010 - POR debug mode status register */ - char res1[12]; + uint pordevsr2; /* 0xe0014 - POR I/O device status regsiter 2 */ +/* The 8544 RM says this is bit 26, but it's really bit 24 */ +#define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080 + char res1[8]; uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */ char res2[12]; uint gpiocr; /* 0xe0030 - GPIO control register */ char res3[12]; +#if defined(CONFIG_MPC8569) + uint plppar1; + /* 0xe0040 - Platform port pin assignment register 1 */ + uint plppar2; + /* 0xe0044 - Platform port pin assignment register 2 */ + uint plpdir1; + /* 0xe0048 - Platform port pin direction register 1 */ + uint plpdir2; + /* 0xe004c - Platform port pin direction register 2 */ +#else uint gpoutdr; /* 0xe0040 - General-purpose output data register */ char res4[12]; +#endif uint gpindr; /* 0xe0050 - General-purpose input data register */ char res5[12]; uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */ +#define MPC85xx_PMUXCR_SD_DATA 0x80000000 +#define MPC85xx_PMUXCR_SDHC_CD 0x40000000 +#define MPC85xx_PMUXCR_SDHC_WP 0x20000000 char res6[12]; uint devdisr; /* 0xe0070 - Device disable control */ #define MPC85xx_DEVDISR_PCI1 0x80000000 @@ -1591,13 +1654,13 @@ typedef struct ccsr_gur { #define MPC85xx_DEVDISR_SEC 0x01000000 #define MPC85xx_DEVDISR_SRIO 0x00080000 #define MPC85xx_DEVDISR_RMSG 0x00040000 -#define MPC85xx_DEVDISR_DDR 0x00010000 -#define MPC85xx_DEVDISR_CPU 0x00008000 -#define MPC85xx_DEVDISR_CPU0 MPC85xx_DEVDISR_CPU -#define MPC85xx_DEVDISR_TB 0x00004000 -#define MPC85xx_DEVDISR_TB0 MPC85xx_DEVDISR_TB -#define MPC85xx_DEVDISR_CPU1 0x00002000 -#define MPC85xx_DEVDISR_TB1 0x00001000 +#define MPC85xx_DEVDISR_DDR 0x00010000 +#define MPC85xx_DEVDISR_CPU 0x00008000 +#define MPC85xx_DEVDISR_CPU0 MPC85xx_DEVDISR_CPU +#define MPC85xx_DEVDISR_TB 0x00004000 +#define MPC85xx_DEVDISR_TB0 MPC85xx_DEVDISR_TB +#define MPC85xx_DEVDISR_CPU1 0x00002000 +#define MPC85xx_DEVDISR_TB1 0x00001000 #define MPC85xx_DEVDISR_DMA 0x00000400 #define MPC85xx_DEVDISR_TSEC1 0x00000080 #define MPC85xx_DEVDISR_TSEC2 0x00000040 @@ -1614,7 +1677,7 @@ typedef struct ccsr_gur { uint svr; /* 0xe00a4 - System version register */ char res10a[8]; uint rstcr; /* 0xe00b0 - Reset control register */ -#ifdef CONFIG_MPC8568 +#if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569) char res10b[76]; par_io_t qe_par_io[7]; /* 0xe0100 - 0xe01bf */ char res10c[3136]; @@ -1630,34 +1693,44 @@ typedef struct ccsr_gur { uint lbiuiplldcr0; /* 0xe0f1c -- LBIU PLL Debug Reg 0 */ uint lbiuiplldcr1; /* 0xe0f20 -- LBIU PLL Debug Reg 1 */ uint ddrioovcr; /* 0xe0f24 - DDR IO Override Control */ - uint res14; /* 0xe0f28 */ + uint tsec12ioovcr; /* 0xe0f28 - eTSEC 1/2 IO override control */ uint tsec34ioovcr; /* 0xe0f2c - eTSEC 3/4 IO override control */ char res15[61648]; /* 0xe0f30 to 0xefffff */ } ccsr_gur_t; -#define PORDEVSR_PCI (0x00800000) /* PCI Mode */ - -#define CFG_MPC85xx_GUTS_OFFSET (0xE0000) -#define CFG_MPC85xx_GUTS_ADDR (CFG_IMMR + CFG_MPC85xx_GUTS_OFFSET) -#define CFG_MPC85xx_ECM_OFFSET (0x0000) -#define CFG_MPC85xx_ECM_ADDR (CFG_IMMR + CFG_MPC85xx_ECM_OFFSET) -#define CFG_MPC85xx_DDR_OFFSET (0x2000) -#define CFG_MPC85xx_DDR_ADDR (CFG_IMMR + CFG_MPC85xx_DDR_OFFSET) -#define CFG_MPC85xx_DDR2_OFFSET (0x6000) -#define CFG_MPC85xx_DDR2_ADDR (CFG_IMMR + CFG_MPC85xx_DDR2_OFFSET) -#define CFG_MPC85xx_LBC_OFFSET (0x5000) -#define CFG_MPC85xx_LBC_ADDR (CFG_IMMR + CFG_MPC85xx_LBC_OFFSET) -#define CFG_MPC85xx_PCIX_OFFSET (0x8000) -#define CFG_MPC85xx_PCIX_ADDR (CFG_IMMR + CFG_MPC85xx_PCIX_OFFSET) -#define CFG_MPC85xx_PCIX2_OFFSET (0x9000) -#define CFG_MPC85xx_PCIX2_ADDR (CFG_IMMR + CFG_MPC85xx_PCIX2_OFFSET) -#define CFG_MPC85xx_L2_OFFSET (0x20000) -#define CFG_MPC85xx_L2_ADDR (CFG_IMMR + CFG_MPC85xx_L2_OFFSET) -#define CFG_MPC85xx_DMA_OFFSET (0x21000) -#define CFG_MPC85xx_DMA_ADDR (CFG_IMMR + CFG_MPC85xx_DMA_OFFSET) -#define CFG_MPC85xx_PIC_OFFSET (0x40000) -#define CFG_MPC85xx_PIC_ADDR (CFG_IMMR + CFG_MPC85xx_PIC_OFFSET) -#define CFG_MPC85xx_CPM_OFFSET (0x80000) -#define CFG_MPC85xx_CPM_ADDR (CFG_IMMR + CFG_MPC85xx_CPM_OFFSET) +#define CONFIG_SYS_MPC85xx_GUTS_OFFSET (0xE0000) +#define CONFIG_SYS_MPC85xx_GUTS_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET) +#define CONFIG_SYS_MPC85xx_ECM_OFFSET (0x0000) +#define CONFIG_SYS_MPC85xx_ECM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET) +#define CONFIG_SYS_MPC85xx_DDR_OFFSET (0x2000) +#define CONFIG_SYS_MPC85xx_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR_OFFSET) +#define CONFIG_SYS_MPC85xx_DDR2_OFFSET (0x6000) +#define CONFIG_SYS_MPC85xx_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET) +#define CONFIG_SYS_MPC85xx_LBC_OFFSET (0x5000) +#define CONFIG_SYS_MPC85xx_LBC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET) +#define CONFIG_SYS_MPC85xx_ESPI_OFFSET (0x7000) +#define CONFIG_SYS_MPC85xx_ESPI_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET) +#define CONFIG_SYS_MPC85xx_PCIX_OFFSET (0x8000) +#define CONFIG_SYS_MPC85xx_PCIX_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET) +#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET (0x9000) +#define CONFIG_SYS_MPC85xx_PCIX2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET) +#define CONFIG_SYS_MPC85xx_SATA1_OFFSET (0x18000) +#define CONFIG_SYS_MPC85xx_SATA1_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET) +#define CONFIG_SYS_MPC85xx_SATA2_OFFSET (0x19000) +#define CONFIG_SYS_MPC85xx_SATA2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET) +#define CONFIG_SYS_MPC85xx_L2_OFFSET (0x20000) +#define CONFIG_SYS_MPC85xx_L2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET) +#define CONFIG_SYS_MPC85xx_DMA_OFFSET (0x21000) +#define CONFIG_SYS_MPC85xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET) +#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET (0x2e000) +#define CONFIG_SYS_MPC85xx_ESDHC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET) +#define CONFIG_SYS_MPC85xx_PIC_OFFSET (0x40000) +#define CONFIG_SYS_MPC85xx_PIC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET) +#define CONFIG_SYS_MPC85xx_CPM_OFFSET (0x80000) +#define CONFIG_SYS_MPC85xx_CPM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET) +#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET (0xE3000) +#define CONFIG_SYS_MPC85xx_SERDES1_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET) +#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET (0xE3100) +#define CONFIG_SYS_MPC85xx_SERDES2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET) #endif /*__IMMAP_85xx__*/