X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fasm-ppc%2Fprocessor.h;h=388dea430c44364b654a457735c2d8f08e852422;hb=2ba20ec65a23ec3a5f1f09e552f2082d841c4031;hp=14b92825cd783f01e598d8918e854f99cea4f447;hpb=e862ed1c22a9aa79835fc4b5f57b4261196a7fac;p=u-boot

diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index 14b92825cd..388dea430c 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -264,7 +264,7 @@
 #define SPRN_ICTC	0x3FB	/* Instruction Cache Throttling Control Reg */
 #define SPRN_IMISS	0x3D4	/* Instruction TLB Miss Register */
 #define SPRN_IMMR	0x27E  	/* Internal Memory Map Register */
-#define SPRN_LDSTCR     0x3F8   /* Load/Store Control Register */
+#define SPRN_LDSTCR	0x3F8   /* Load/Store Control Register */
 #define SPRN_L2CR	0x3F9	/* Level 2 Cache Control Regsiter */
 #define SPRN_LR		0x008	/* Link Register */
 #define SPRN_MBAR       0x137   /* System memory base address */
@@ -445,7 +445,7 @@
 #define ESR_ST          0x00800000      /* Store Operation */
 
 #if defined(CONFIG_MPC86xx)
-#define SPRN_MSSCRO     0x3f6
+#define SPRN_MSSCRO	0x3f6
 #endif
 
 
@@ -507,12 +507,12 @@
 #define ICMP	SPRN_ICMP	/* Instruction TLB Compare Register */
 #define IMISS	SPRN_IMISS	/* Instruction TLB Miss Register */
 #define IMMR	SPRN_IMMR      	/* PPC 860/821 Internal Memory Map Register */
-#define LDSTCR  SPRN_LDSTCR     /* Load/Store Control Register */
+#define LDSTCR	SPRN_LDSTCR     /* Load/Store Control Register */
 #define L2CR	SPRN_L2CR    	/* PPC 750 L2 control register */
 #define LR	SPRN_LR
 #define MBAR    SPRN_MBAR       /* System memory base address */
 #if defined(CONFIG_MPC86xx)
-#define MSSCR0  SPRN_MSSCRO
+#define MSSCR0	SPRN_MSSCRO
 #endif
 #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
 #define PIR	SPRN_PIR
@@ -548,7 +548,7 @@
 #define CSRR0	SPRN_CSRR0
 #define CSRR1	SPRN_CSRR1
 #define IVPR	SPRN_IVPR
-#define USPRG0 SPRN_USPRG
+#define USPRG0	SPRN_USPRG
 #define SPRG4R	SPRN_SPRG4R
 #define SPRG5R	SPRN_SPRG5R
 #define SPRG6R	SPRN_SPRG6R
@@ -738,6 +738,10 @@
 #define PVR_440EP_RC	0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */
 #define PVR_440GR_RA	0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */
 #define PVR_440GR_RB	0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */
+#define PVR_440EPX1_RA  0x216218D0 /* 440EPX rev A with Security / Kasumi */
+#define PVR_440EPX2_RA  0x216218D4 /* 440EPX rev A without Security / Kasumi */
+#define PVR_440GRX1_RA  0x216218D8 /* 440GRX rev A with Security / Kasumi */
+#define PVR_440GRX2_RA  0x216218DC /* 440GRX rev A without Security / Kasumi */
 #define PVR_440GX_RA	0x51B21850
 #define PVR_440GX_RB	0x51B21851
 #define PVR_440GX_RC	0x51B21892
@@ -806,6 +810,8 @@
 #define SVR_VER(svr)	(((svr) >>  16) & 0xFFFF)	/* Version field */
 #define SVR_REV(svr)	(((svr) >>   0) & 0xFFFF)	/* Revison field */
 
+#define SVR_SUBVER(svr)	(((svr) >>  8) & 0xFF)	/* Process/MFG sub-version */
+
 #define SVR_FAM(svr)	(((svr) >> 20) & 0xFFF)	/* Family field */
 #define SVR_MEM(svr)	(((svr) >> 16) & 0xF)	/* Member field */
 
@@ -823,9 +829,8 @@
 #define SVR_8541	0x807A
 #define SVR_8548	0x8031
 #define SVR_8548_E	0x8039
-
 #define SVR_8641	0x8090
-#define SVR_8641D	0x8091
+
 
 /* I am just adding a single entry for 8260 boards.  I think we may be
  * able to combine mbx, fads, rpxlite, bseip, and classic into a single