X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fasm-ppc%2Fprocessor.h;h=9a9b8ba7161ad7348be9b3d6c2cfbb11087f07c9;hb=6c5879f380be38d85fef0d3aba3353358f4b2ff4;hp=d4404c129534b494b0564bef1a1f77de96902f44;hpb=a720fd99b614ba36293565771bcd19799bc53959;p=u-boot

diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index d4404c1295..9a9b8ba716 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -310,10 +310,10 @@
 #define SPRN_TBHU	0x3CC	/* Time Base High User-mode */
 #define SPRN_TBLO	0x3DD	/* Time Base Low */
 #define SPRN_TBLU	0x3CD	/* Time Base Low User-mode */
-#define SPRN_TBRL	0x10D	/* Time Base Read Lower Register */
-#define SPRN_TBRU	0x10C	/* Time Base Read Upper Register */
-#define SPRN_TBWL	0x11D	/* Time Base Write Lower Register */
-#define SPRN_TBWU	0x11C	/* Time Base Write Upper Register */
+#define SPRN_TBRL	0x10C	/* Time Base Read Lower Register */
+#define SPRN_TBRU	0x10D	/* Time Base Read Upper Register */
+#define SPRN_TBWL	0x11C	/* Time Base Write Lower Register */
+#define SPRN_TBWU	0x11D	/* Time Base Write Upper Register */
 #ifndef CONFIG_BOOKE
 #define SPRN_TCR	0x3DA	/* Timer Control Register */
 #else
@@ -694,7 +694,7 @@
 #define PVR_REV(pvr)  (((pvr) >>   0) & 0xFFFF)	/* Revison field */
 
 /*
- * IBM has further subdivided the standard PowerPC 16-bit version and
+ * AMCC has further subdivided the standard PowerPC 16-bit version and
  * revision subfields of the PVR for the PowerPC 403s into the following:
  */
 
@@ -723,10 +723,18 @@
 #define PVR_405GPR_RB	0x50910951
 #define PVR_440GP_RB	0x40120440
 #define PVR_440GP_RC	0x40120481
+#define PVR_440EP_RA	0x42221850
+#define PVR_440EP_RB	0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */
+#define PVR_440GR_RA	0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */
 #define PVR_440GX_RA	0x51B21850
 #define PVR_440GX_RB	0x51B21851
 #define PVR_440GX_RC	0x51B21892
+#define PVR_440GX_RF	0x51B21894
 #define PVR_405EP_RB	0x51210950
+#define PVR_440SP_RA	0x53221850
+#define PVR_440SP_RB	0x53221891
+#define PVR_440SPe_RA	0x53421890
+#define PVR_440SPe_RB	0x53521891
 #define PVR_601		0x00010000
 #define PVR_602		0x00050000
 #define PVR_603		0x00030000
@@ -823,7 +831,7 @@
 #define _MACH_gemini	0x00000200	/* Synergy Microsystems gemini board */
 #define _MACH_classic	0x00000400	/* RPCG RPX-Classic 8xx board */
 #define _MACH_oak	0x00000800	/* IBM "Oak" 403 eval. board */
-#define _MACH_walnut	0x00001000	/* IBM "Walnut" 405GP eval. board */
+#define _MACH_walnut	0x00001000	/* AMCC "Walnut" 405GP eval. board */
 #define _MACH_8260	0x00002000	/* Generic 8260 */
 #define _MACH_sandpoint 0x00004000	/* Motorola SPS Processor eval board */
 #define _MACH_tqm860	0x00008000	/* TQM860/L */