X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fasm-sh%2Fcache.h;h=2cfc0a79447c4ca8f5373a34b10017b9815ca4c5;hb=7d6900ebe16d679c0e03f8d1584b64057a64ce39;hp=67474c7b4404c91c81117ab52c93847d5e7f8cda;hpb=2c78febd114b716714e7ac83c17bac5e30066512;p=u-boot

diff --git a/include/asm-sh/cache.h b/include/asm-sh/cache.h
index 67474c7b44..2cfc0a7944 100644
--- a/include/asm-sh/cache.h
+++ b/include/asm-sh/cache.h
@@ -3,32 +3,32 @@
 
 #if defined(CONFIG_SH4) || defined(CONFIG_SH4A)
 
+int cache_control(unsigned int cmd);
+
 #define L1_CACHE_BYTES 32
 struct __large_struct { unsigned long buf[100]; };
 #define __m(x) (*(struct __large_struct *)(x))
 
 void dcache_wback_range(u32 start, u32 end)
 {
-    u32 v;
-
-    start &= ~(L1_CACHE_BYTES-1);
-    for (v = start; v < end; v+=L1_CACHE_BYTES) {
-        asm volatile("ocbwb     %0"
-                     : /* no output */
-                     : "m" (__m(v)));
-    }
+	u32 v;
+
+	start &= ~(L1_CACHE_BYTES - 1);
+	for (v = start; v < end; v += L1_CACHE_BYTES) {
+		asm volatile ("ocbwb     %0" :	/* no output */
+			      : "m" (__m(v)));
+	}
 }
 
 void dcache_invalid_range(u32 start, u32 end)
 {
-    u32 v;
-
-    start &= ~(L1_CACHE_BYTES-1);
-    for (v = start; v < end; v+=L1_CACHE_BYTES) {
-        asm volatile("ocbi     %0"
-                     : /* no output */
-                     : "m" (__m(v)));
-    }
+	u32 v;
+
+	start &= ~(L1_CACHE_BYTES - 1);
+	for (v = start; v < end; v += L1_CACHE_BYTES) {
+		asm volatile ("ocbi     %0" :	/* no output */
+			      : "m" (__m(v)));
+	}
 }
 #endif /* CONFIG_SH4 || CONFIG_SH4A */