X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fcommproc.h;h=12decfeaa57abb3b61492a7370073e58e00275c8;hb=e05825324a8a7679b87db550a0d7ade06c890494;hp=83119717a9c30377d8e654b17bbe1f6f734214bf;hpb=281e00a3be453a169d854f824a460359d10f92bb;p=u-boot diff --git a/include/commproc.h b/include/commproc.h index 83119717a9..12decfeaa5 100644 --- a/include/commproc.h +++ b/include/commproc.h @@ -2,7 +2,7 @@ * MPC8xx Communication Processor Module. * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) * - * (C) Copyright 2000-2004 + * (C) Copyright 2000-2006 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * This file contains structures and information for the communication @@ -62,7 +62,7 @@ * as data ram for buffer descriptors, which is all we use right now. * Currently the first 512 and last 256 bytes are used for microcode. */ -#ifdef CFG_ALLOC_DPRAM +#ifdef CONFIG_SYS_ALLOC_DPRAM #define CPM_DATAONLY_BASE ((uint)0x0800) #define CPM_DATAONLY_SIZE ((uint)0x0700) @@ -74,23 +74,23 @@ #define CPM_I2C_BASE 0x0820 #define CPM_SPI_BASE 0x0840 #define CPM_FEC_BASE 0x0860 -#define CPM_SERIAL2_BASE 0x0880 +#define CPM_SERIAL2_BASE 0x08E0 #define CPM_SCC_BASE 0x0900 #define CPM_POST_BASE 0x0980 #define CPM_WLKBD_BASE 0x0a00 #endif -#ifndef CFG_CPM_POST_WORD_ADDR +#ifndef CONFIG_SYS_CPM_POST_WORD_ADDR #define CPM_POST_WORD_ADDR 0x07FC #else -#define CPM_POST_WORD_ADDR CFG_CPM_POST_WORD_ADDR +#define CPM_POST_WORD_ADDR CONFIG_SYS_CPM_POST_WORD_ADDR #endif -#ifndef CFG_CPM_BOOTCOUNT_ADDR +#ifndef CONFIG_SYS_CPM_BOOTCOUNT_ADDR #define CPM_BOOTCOUNT_ADDR (CPM_POST_WORD_ADDR - 2*sizeof(ulong)) #else -#define CPM_BOOTCOUNT_ADDR CFG_CPM_BOOTCOUNT_ADDR +#define CPM_BOOTCOUNT_ADDR CONFIG_SYS_CPM_BOOTCOUNT_ADDR #endif #define BD_IIC_START ((uint) 0x0400) /* <- please use CPM_I2C_BASE !! */ @@ -159,6 +159,8 @@ typedef struct smc_uart { ushort smc_brkec; /* rcv'd break condition counter */ ushort smc_brkcr; /* xmt break count register */ ushort smc_rmask; /* Temporary bit mask */ + u_char res1[8]; + ushort smc_rpbase; /* Relocation pointer */ } smc_uart_t; /* Function code bits. @@ -784,19 +786,19 @@ typedef struct scc_enet { #undef SCC_ENET #define FEC_ENET -#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ -#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ -#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ -#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ -#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ -#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ -#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ -#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ -#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ -#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ -#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ -#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ -#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ +#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ +#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ +#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ +#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ +#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ +#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ +#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ +#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ +#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ +#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ +#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ +#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ +#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ #define PD_MII_MASK ((ushort)0x1FFF) /* PD 3-15 */ #endif /* CONFIG_GEN860T */ @@ -1120,6 +1122,32 @@ typedef struct scc_enet { #define SICR_ENET_CLKRT ((uint)0x0000003d) #endif /* CONFIG_MBX */ +/*** MGSUVD *********************************************************/ + +/* The MGSUVD Service Module uses SCC3 for Ethernet */ + +#ifdef CONFIG_MGSUVD +#define PROFF_ENET PROFF_SCC3 /* Ethernet on SCC3 */ +#define CPM_CR_ENET CPM_CR_CH_SCC3 +#define SCC_ENET 2 +#define PA_ENET_RXD ((ushort)0x0010) /* PA 11 */ +#define PA_ENET_TXD ((ushort)0x0020) /* PA 10 */ +#define PA_ENET_RCLK ((ushort)0x1000) /* PA 3 CLK 5 */ +#define PA_ENET_TCLK ((ushort)0x2000) /* PA 2 CLK 6 */ + +#define PC_ENET_TENA ((ushort)0x0004) /* PC 13 */ + +#define PC_ENET_RENA ((ushort)0x0200) /* PC 6 */ +#define PC_ENET_CLSN ((ushort)0x0100) /* PC 7 */ + +/* Control bits in the SICR to route TCLK (CLK6) and RCLK (CLK5) to + * SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero. + */ +#define SICR_ENET_MASK ((uint)0x00FF0000) +#define SICR_ENET_CLKRT ((uint)0x00250000) +#endif /* CONFIG_MGSUVD */ + + /*** MHPC ********************************************************/ #if defined(CONFIG_MHPC) @@ -1405,20 +1433,24 @@ typedef struct scc_enet { #endif /* CONFIG_SXNI855T */ -/*** MVS1, TQM823L/M, TQM850L/M, ETX094, R360MPI *******************/ +/*** MVS1, TQM823L/M, TQM850L/M, TQM885D, ETX094, R360MPI **********/ #if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \ defined(CONFIG_R360MPI) || defined(CONFIG_RBC823) || \ defined(CONFIG_TQM823L) || defined(CONFIG_TQM823M) || \ defined(CONFIG_TQM850L) || defined(CONFIG_TQM850M) || \ - defined(CONFIG_ETX094) || defined(CONFIG_RRVISION)|| \ + defined(CONFIG_TQM885D) || defined(CONFIG_ETX094) || \ + defined(CONFIG_RRVISION)|| defined(CONFIG_VIRTLAB2)|| \ (defined(CONFIG_LANTEC) && CONFIG_LANTEC < 2) + /* Bits in parallel I/O port registers that have to be set/cleared * to configure the pins for SCC2 use. */ #define PROFF_ENET PROFF_SCC2 #define CPM_CR_ENET CPM_CR_CH_SCC2 +#if (!defined(CONFIG_TK885D)) /* TK885D does not use SCC Ethernet */ #define SCC_ENET 1 +#endif #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ #define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ @@ -1437,6 +1469,11 @@ typedef struct scc_enet { */ #define SICR_ENET_MASK ((uint)0x0000ff00) #define SICR_ENET_CLKRT ((uint)0x00002600) + +# ifdef CONFIG_FEC_ENET /* Use FEC for Fast Ethernet */ +#define FEC_ENET +# endif /* CONFIG_FEC_ENET */ + #endif /* CONFIG_MVS v1, CONFIG_TQM823L/M, CONFIG_TQM850L/M, etc. */ /*** TQM855L/M, TQM860L/M, TQM862L/M, TQM866L/M *********************/