X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fcommproc.h;h=32a3e1c82a84bbdf59e20720fed94ff889090b89;hb=10212a0f11dc3b63cc8960c62ea91b519cb4793f;hp=c10525d4e874d9aa66993de83a858e9565fbc049;hpb=993cad9364c6b87ae429d1ed1130d8153f6f027e;p=u-boot

diff --git a/include/commproc.h b/include/commproc.h
index c10525d4e8..32a3e1c82a 100644
--- a/include/commproc.h
+++ b/include/commproc.h
@@ -2,6 +2,9 @@
  * MPC8xx Communication Processor Module.
  * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
  *
+ * (C) Copyright 2000-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
  * This file contains structures and information for the communication
  * processor channels.  Some CPM control and status is available
  * throught the MPC8xx internal memory map.  See immap.h for details.
@@ -71,9 +74,10 @@
 #define CPM_I2C_BASE		0x0820
 #define CPM_SPI_BASE		0x0840
 #define CPM_FEC_BASE		0x0860
-#define CPM_WLKBD_BASE		0x0880
+#define CPM_SERIAL2_BASE	0x08E0
 #define CPM_SCC_BASE		0x0900
 #define CPM_POST_BASE		0x0980
+#define CPM_WLKBD_BASE		0x0a00
 
 #endif
 
@@ -83,6 +87,12 @@
 #define CPM_POST_WORD_ADDR	CFG_CPM_POST_WORD_ADDR
 #endif
 
+#ifndef CFG_CPM_BOOTCOUNT_ADDR
+#define CPM_BOOTCOUNT_ADDR	(CPM_POST_WORD_ADDR - 2*sizeof(ulong))
+#else
+#define CPM_BOOTCOUNT_ADDR	CFG_CPM_BOOTCOUNT_ADDR
+#endif
+
 #define BD_IIC_START	((uint) 0x0400) /* <- please use CPM_I2C_BASE !! */
 
 /* Export the base address of the communication processor registers
@@ -149,6 +159,8 @@ typedef struct smc_uart {
 	ushort	smc_brkec;	/* rcv'd break condition counter */
 	ushort	smc_brkcr;	/* xmt break count register */
 	ushort	smc_rmask;	/* Temporary bit mask */
+	u_char	res1[8];
+	ushort	smc_rpbase;	/* Relocation pointer */
 } smc_uart_t;
 
 /* Function code bits.
@@ -707,13 +719,14 @@ typedef struct scc_enet {
 
 /***  FADS860T********************************************************/
 
-#if defined(CONFIG_MPC860T) && defined(CONFIG_FADS)
-/* This ENET stuff is for the MPC860TFADS with ethernet on SCC1.
+#if defined(CONFIG_FADS) && defined(CONFIG_MPC86x)
+/*
+ * This ENET stuff is for the MPC86xFADS/MPC8xxADS with ethernet on SCC1.
  */
-
 #ifdef CONFIG_SCC1_ENET
+
 #define	SCC_ENET	0
-#endif	/* CONFIG_SCC1_ETHERNET */
+
 #define	PROFF_ENET	PROFF_SCC1
 #define	CPM_CR_ENET	CPM_CR_CH_SCC1
 
@@ -730,14 +743,18 @@ typedef struct scc_enet {
 #define SICR_ENET_MASK	((uint)0x000000ff)
 #define SICR_ENET_CLKRT	((uint)0x0000002c)
 
-/* This ENET stuff is for the MPC860TFADS with ethernet on FEC.
+#endif	/* CONFIG_SCC1_ETHERNET */
+
+/*
+ * This ENET stuff is for the MPC860TFADS/MPC86xADS/MPC885ADS
+ * with ethernet on FEC.
  */
 
 #ifdef CONFIG_FEC_ENET
-#define	FEC_ENET	/* use FEC for EThernet */
-#endif	/* CONFIG_FEC_ETHERNET */
+#define	FEC_ENET	/* Use FEC for Ethernet */
+#endif	/* CONFIG_FEC_ENET */
 
-#endif	/* CONFIG_FADS860T */
+#endif	/* CONFIG_FADS && CONFIG_MPC86x */
 
 /***  FPS850L, FPS860L  ************************************************/
 
@@ -967,10 +984,10 @@ typedef struct scc_enet {
 
 #endif	/* CONFIG_IVMS8, CONFIG_IVML24 */
 
-/***  KUP4K  *********************************************************/
-/* The KUP4K uses the FEC on a MPC855T for Ethernet */
+/***  KUP4K, KUP4X ****************************************************/
+/* The KUP4 boards uses the FEC on a MPC8xx for Ethernet */
 
-#if defined(CONFIG_KUP4K)
+#if defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X)
 
 #define	FEC_ENET	/* use FEC for EThernet */
 #undef	SCC_ENET
@@ -1027,7 +1044,7 @@ typedef struct scc_enet {
 
 /***  LWMON  **********************************************************/
 
-#if defined(CONFIG_LWMON) && !defined(CONFIG_8xx_CONS_SCC2)
+#if defined(CONFIG_LWMON)
 /* Bits in parallel I/O port registers that have to be set/cleared
  * to configure the pins for SCC2 use.
  */
@@ -1105,6 +1122,32 @@ typedef struct scc_enet {
 #define SICR_ENET_CLKRT	((uint)0x0000003d)
 #endif	/* CONFIG_MBX */
 
+/***  MGSUVD  *********************************************************/
+
+/* The MGSUVD Service Module uses SCC3 for Ethernet */
+
+#ifdef CONFIG_MGSUVD
+#define PROFF_ENET	PROFF_SCC3		/* Ethernet on SCC3 */
+#define CPM_CR_ENET	CPM_CR_CH_SCC3
+#define SCC_ENET	2
+#define PA_ENET_RXD	((ushort)0x0010)	/* PA 11 */
+#define PA_ENET_TXD	((ushort)0x0020)	/* PA 10 */
+#define PA_ENET_RCLK	((ushort)0x1000)	/* PA  3 CLK 5 */
+#define PA_ENET_TCLK	((ushort)0x2000)	/* PA  2 CLK 6 */
+
+#define PC_ENET_TENA	((ushort)0x0004)	/* PC 13 */
+
+#define PC_ENET_RENA	((ushort)0x0200)	/* PC  6 */
+#define PC_ENET_CLSN	((ushort)0x0100)	/* PC  7 */
+
+/* Control bits in the SICR to route TCLK (CLK6) and RCLK (CLK5) to
+ * SCC3.  Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero.
+ */
+#define SICR_ENET_MASK	((uint)0x00FF0000)
+#define SICR_ENET_CLKRT	((uint)0x00250000)
+#endif	/* CONFIG_MGSUVD */
+
+
 /***  MHPC  ********************************************************/
 
 #if defined(CONFIG_MHPC)
@@ -1177,8 +1220,8 @@ typedef struct scc_enet {
 
 # endif /* CONFIG_FEC_ENET */
 #endif  /* CONFIG_SVM_SC8xx */
-	
-	
+
+
 #if defined(CONFIG_NETVIA)
 /* Bits in parallel I/O port registers that have to be set/cleared
  * to configure the pins for SCC2 use.
@@ -1210,6 +1253,60 @@ typedef struct scc_enet {
 
 #endif	/* CONFIG_NETVIA */
 
+/***  QS850/QS823  ***************************************************/
+
+#if defined(CONFIG_QS850) || defined(CONFIG_QS823)
+#undef FEC_ENET /* Don't use FEC for EThernet */
+
+#define PROFF_ENET		PROFF_SCC2
+#define CPM_CR_ENET		CPM_CR_CH_SCC2
+#define SCC_ENET		1
+
+#define PA_ENET_RXD		((ushort)0x0004)  /* RXD on PA13 (Pin D9) */
+#define PA_ENET_TXD		((ushort)0x0008)  /* TXD on PA12 (Pin D7) */
+#define PC_ENET_RENA		((ushort)0x0080)  /* RENA on PC8 (Pin D12) */
+#define PC_ENET_CLSN		((ushort)0x0040)  /* CLSN on PC9 (Pin C12) */
+#define PA_ENET_TCLK		((ushort)0x0200)  /* TCLK on PA6 (Pin D8) */
+#define PA_ENET_RCLK		((ushort)0x0800)  /* RCLK on PA4 (Pin D10) */
+#define PB_ENET_TENA		((uint)0x00002000)  /* TENA on PB18 (Pin D11) */
+#define PC_ENET_LBK		((ushort)0x0010)  /* Loopback control on PC11 (Pin B14) */
+#define PC_ENET_LI		((ushort)0x0020)  /* Link Integrity control PC10 (A15) */
+#define PC_ENET_SQE		((ushort)0x0100)  /* SQE Disable control PC7 (B15) */
+
+/* SCC2 TXCLK from CLK2
+ * SCC2 RXCLK from CLK4
+ * SCC2 Connected to NMSI */
+#define SICR_ENET_MASK		((uint)0x00007F00)
+#define SICR_ENET_CLKRT		((uint)0x00003D00)
+
+#endif /* CONFIG_QS850/QS823 */
+
+/***  QS860T  ***************************************************/
+
+#ifdef CONFIG_QS860T
+#ifdef CONFIG_FEC_ENET
+#define FEC_ENET /* use FEC for EThernet */
+#endif /* CONFIG_FEC_ETHERNET */
+
+/* This ENET stuff is for GTH 10 Mbit ( SCC ) */
+#define PROFF_ENET		PROFF_SCC1
+#define CPM_CR_ENET		CPM_CR_CH_SCC1
+#define SCC_ENET		0
+
+#define PA_ENET_RXD		((ushort)0x0001) /* PA15 */
+#define PA_ENET_TXD		((ushort)0x0002) /* PA14 */
+#define PA_ENET_TCLK		((ushort)0x0800) /* PA4 */
+#define PA_ENET_RCLK		((ushort)0x0200) /* PA6 */
+#define PB_ENET_TENA		((uint)0x00001000) /* PB19 */
+#define PC_ENET_CLSN		((ushort)0x0010) /* PC11 */
+#define PC_ENET_RENA		((ushort)0x0020) /* PC10 */
+
+#define SICR_ENET_MASK		((uint)0x000000ff)
+/* RCLK PA4 -->CLK4, TCLK PA6 -->CLK2 */
+#define SICR_ENET_CLKRT		((uint)0x0000003D)
+
+#endif /* CONFIG_QS860T */
+
 /***  RPXCLASSIC  *****************************************************/
 
 #ifdef CONFIG_RPXCLASSIC
@@ -1336,20 +1433,24 @@ typedef struct scc_enet {
 
 #endif	/* CONFIG_SXNI855T */
 
-/***  MVS1, TQM823L/M, TQM850L/M, ETX094, R360MPI  *******************/
+/***  MVS1, TQM823L/M, TQM850L/M, TQM885D, ETX094, R360MPI  **********/
 
 #if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \
     defined(CONFIG_R360MPI) || defined(CONFIG_RBC823)  || \
     defined(CONFIG_TQM823L) || defined(CONFIG_TQM823M) || \
     defined(CONFIG_TQM850L) || defined(CONFIG_TQM850M) || \
-    defined(CONFIG_ETX094)  || defined(CONFIG_RRVISION)|| \
+    defined(CONFIG_TQM885D) || defined(CONFIG_ETX094)  || \
+    defined(CONFIG_RRVISION)|| defined(CONFIG_VIRTLAB2)|| \
    (defined(CONFIG_LANTEC) && CONFIG_LANTEC < 2)
+
 /* Bits in parallel I/O port registers that have to be set/cleared
  * to configure the pins for SCC2 use.
  */
 #define	PROFF_ENET	PROFF_SCC2
 #define	CPM_CR_ENET	CPM_CR_CH_SCC2
+#if (!defined(CONFIG_TK885D))	/* TK885D does not use SCC Ethernet */
 #define	SCC_ENET	1
+#endif
 #define PA_ENET_RXD	((ushort)0x0004)	/* PA 13 */
 #define PA_ENET_TXD	((ushort)0x0008)	/* PA 12 */
 #define PA_ENET_RCLK	((ushort)0x0100)	/* PA  7 */
@@ -1368,13 +1469,19 @@ typedef struct scc_enet {
  */
 #define SICR_ENET_MASK	((uint)0x0000ff00)
 #define SICR_ENET_CLKRT	((uint)0x00002600)
+
+# ifdef CONFIG_FEC_ENET		/* Use FEC for Fast Ethernet */
+#define FEC_ENET
+# endif	/* CONFIG_FEC_ENET */
+
 #endif	/* CONFIG_MVS v1, CONFIG_TQM823L/M, CONFIG_TQM850L/M, etc. */
 
-/***  TQM855L/M, TQM860L/M, TQM862L/M  ********************************/
+/***  TQM855L/M, TQM860L/M, TQM862L/M, TQM866L/M  *********************/
 
 #if defined(CONFIG_TQM855L) || defined(CONFIG_TQM855M) || \
     defined(CONFIG_TQM860L) || defined(CONFIG_TQM860M) || \
-    defined(CONFIG_TQM862L) || defined(CONFIG_TQM862M)
+    defined(CONFIG_TQM862L) || defined(CONFIG_TQM862M) || \
+    defined(CONFIG_TQM866L) || defined(CONFIG_TQM866M)
 
 # ifdef CONFIG_SCC1_ENET	/* use SCC for 10Mbps Ethernet	*/
 
@@ -1446,6 +1553,7 @@ typedef struct scc_enet {
 #define SICR_ENET_CLKRT	((uint)0x00002e00)
 #endif	/* CONFIG_V37 */
 
+
 /*********************************************************************/
 
 /* SCC Event register as used by Ethernet.