X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2FATUM8548.h;h=5bc28f18f90a0b1a1e8aed703999bd11262cc761;hb=ac53ee8318678190bf3c68da477a84a657d86fb0;hp=c14376e7f4923b8429f56fed7a951bb5c22e9eb7;hpb=8f00731818f0f0deaca899bde56de98d3d95c0b6;p=u-boot

diff --git a/include/configs/ATUM8548.h b/include/configs/ATUM8548.h
index c14376e7f4..5bc28f18f9 100644
--- a/include/configs/ATUM8548.h
+++ b/include/configs/ATUM8548.h
@@ -55,18 +55,11 @@
 
 #define CONFIG_TSEC_ENET	1	/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
-#define CONFIG_SPD_EEPROM	1 	/* Use SPD EEPROM for DDR setup*/
-#undef CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
 
-#define CONFIG_DDR_ECC			/* only for ECC DDR module */
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
-#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
 #define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */
 
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 
-#define MPC85xx_DDR_SDRAM_CLK_CNTL	/* 85xx has clock control reg */
-
 #define CONFIG_SYS_CLK_FREQ	33000000
 
 /*
@@ -84,7 +77,7 @@
 
 #define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
 
-#define CONFIG_CMD_SDRAM 		1	/* SDRAM DIMM SPD info printout */
+#define CONFIG_CMD_SDRAM		1	/* SDRAM DIMM SPD info printout */
 #define CONFIG_ENABLE_36BIT_PHYS	1
 #undef	CFG_DRAM_TEST
 #define CFG_MEMTEST_START	0x00200000	/* memtest works on */
@@ -96,6 +89,7 @@
  */
 #define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
 #define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
 #define PCI_SPEED		33333000        /* CPLD currenlty does not have PCI setup info */
@@ -103,33 +97,38 @@
 #define CFG_PCI2_ADDR	(CFG_CCSRBAR+0x9000)
 #define CFG_PCIE1_ADDR	(CFG_CCSRBAR+0xa000)
 
-/*
- * DDR Setup
- */
-#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
-#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+/* DDR Setup */
+#define CONFIG_FSL_DDR2
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_DDR_ECC			/* only for ECC DDR module */
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
+#define CONFIG_DDR_SPD
 
-#if defined(CONFIG_SPD_EEPROM)
-    /*
-     * Determine DDR configuration from I2C interface.
-     */
-    #define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
 
-#else
-    /*
-     * Manually set up DDR parameters
-     */
-    #define CFG_SDRAM_SIZE	1024		/* DDR is 1024MB */
-    #define CFG_DDR_CS0_BNDS	0x0000000f	/* 0-1024 */
-    #define CFG_DDR_CS0_CONFIG	0x80000102
-    #define CFG_DDR_TIMING_0	0x00260802
-    #define CFG_DDR_TIMING_1	0x38355322
-    #define CFG_DDR_TIMING_2	0x039048c7
-    #define CFG_DDR_CONTROL	0xc2000000	/* unbuffered,no DYN_PWR */
-    #define CFG_DDR_MODE	0x00000432
-    #define CFG_DDR_INTERVAL	0x05150100
-    #define DDR_SDRAM_CFG	0x43000000
-#endif
+#define CFG_DDR_SDRAM_BASE	0x00000000
+#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
+
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	2
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
+
+/* Manually set up DDR parameters */
+#define CFG_SDRAM_SIZE	1024		/* DDR is 1024MB */
+#define CFG_DDR_CS0_BNDS	0x0000000f	/* 0-1024 */
+#define CFG_DDR_CS0_CONFIG	0x80000102
+#define CFG_DDR_TIMING_0	0x00260802
+#define CFG_DDR_TIMING_1	0x38355322
+#define CFG_DDR_TIMING_2	0x039048c7
+#define CFG_DDR_CONTROL	0xc2000000	/* unbuffered,no DYN_PWR */
+#define CFG_DDR_MODE	0x00000432
+#define CFG_DDR_INTERVAL	0x05150100
+#define DDR_SDRAM_CFG	0x43000000
 
 #undef CONFIG_CLOCKS_IN_MHZ
 
@@ -181,7 +180,7 @@
 
 #define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 
-#define CFG_FLASH_CFI_DRIVER    1
+#define CONFIG_FLASH_CFI_DRIVER    1
 #define CFG_FLASH_CFI           1
 #define CFG_FLASH_EMPTY_INFO
 
@@ -275,7 +274,7 @@
 #if !defined(CONFIG_PCI_PNP)
     #define PCI_ENET0_IOADDR	0xe0000000
     #define PCI_ENET0_MEMADDR	0xe0000000
-    #define PCI_IDSEL_NUMBER	0x0c 	/* slot0->3(IDSEL)=12->15 */
+    #define PCI_IDSEL_NUMBER	0x0c	/* slot0->3(IDSEL)=12->15 */
 #endif
 
 #if defined(CONFIG_PCI)