X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2FBC3450.h;h=8a73a9a4c08f39ccdd7eaefd7d2a0f7d6b3ce898;hb=ed97abed27455b4f9e0dec6274976f5010258ed9;hp=44befe9edfa09793e3050e582851b6002a602acc;hpb=fd428c05c863aefb575b12b2a1916b02d5bfa759;p=u-boot

diff --git a/include/configs/BC3450.h b/include/configs/BC3450.h
index 44befe9edf..8a73a9a4c0 100644
--- a/include/configs/BC3450.h
+++ b/include/configs/BC3450.h
@@ -56,10 +56,17 @@
 #define CONFIG_BC3450_FP	1	/*  + enable FP O/P		    */
 #undef CONFIG_BC3450_CRT		/*  + enable CRT O/P (Debug only!)  */
 
-#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz	    */
+/*
+ * Valid values for CONFIG_SYS_TEXT_BASE are:
+ * 0xFC000000	boot low (standard configuration with room for
+ *		max 64 MByte Flash ROM)
+ * 0x00100000	boot from RAM (for testing only)
+ */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xFC000000
+#endif
 
-#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM		0x02	/* Software reboot		    */
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz	    */
 
 #define CONFIG_HIGH_BATS	1	/* High BATs supported		    */
 
@@ -99,7 +106,6 @@
 #define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
 #define CONFIG_PCI_IO_SIZE	0x01000000
 
-#define CONFIG_NET_MULTI	1
 /*#define CONFIG_EEPRO100	XXX - FIXME: conflicts when CONFIG_MII is enabled */
 #define CONFIG_SYS_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100	*/
 #define CONFIG_NS8382X		1
@@ -207,7 +213,7 @@
 
 #define CONFIG_TIMESTAMP		/* display image timestamps */
 
-#if (TEXT_BASE == 0xFC000000)		/* Boot low */
+#if (CONFIG_SYS_TEXT_BASE == 0xFC000000)		/* Boot low */
 #   define CONFIG_SYS_LOWBOOT		1
 #endif
 
@@ -324,7 +330,7 @@
 /*
  * Flash configuration
  */
-#define CONFIG_SYS_FLASH_BASE		TEXT_BASE /* 0xFC000000 */
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_TEXT_BASE /* 0xFC000000 */
 
 /* use CFI flash driver if no module variant is spezified */
 #define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
@@ -377,16 +383,15 @@
 #define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
 #ifdef CONFIG_POST
 /* preserve space for the post_word at end of on-chip SRAM */
-# define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
+# define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_POST_SIZE
 #else
-# define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE
+# define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
 #endif /*CONFIG_POST*/
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* Bytes reserved for initial data  */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 #   define CONFIG_SYS_RAMBOOT		1
 #endif