X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2FC29XPCIE.h;h=69a9798540efe1c33fd8674abcd71587f7327194;hb=63865278dae47ad19527d9f9b6e0dad6cb01f401;hp=9e12fac5b13315850216f9b65eb3707181778f2a;hpb=d2a3e911390f9fc4d8c0ee4b3c7fc75f4fd3fd19;p=u-boot diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index 9e12fac5b1..69a9798540 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -12,6 +12,7 @@ #define __CONFIG_H #define CONFIG_PHYS_64BIT +#define CONFIG_DISPLAY_BOARDINFO #ifdef CONFIG_C29XPCIE #define CONFIG_PPC_C29X @@ -24,8 +25,6 @@ #endif #ifdef CONFIG_NAND -#define CONFIG_SPL -#define CONFIG_TPL #ifdef CONFIG_TPL_BUILD #define CONFIG_SPL_NAND_BOOT #define CONFIG_SPL_FLUSH_IMAGE @@ -88,21 +87,19 @@ #define CONFIG_BOOKE /* BOOKE */ #define CONFIG_E500 /* BOOKE e500 family */ #define CONFIG_FSL_IFC /* Enable IFC Support */ +#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ #define CONFIG_PCI /* Enable PCI/PCIE */ #ifdef CONFIG_PCI -#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ +#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ -#define CONFIG_CMD_NET #define CONFIG_CMD_PCI -#define CONFIG_E1000 - /* * PCI Windows * Memory space is mapped 1-1, but I/O space must start from 0. @@ -233,7 +230,6 @@ #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024) @@ -319,7 +315,7 @@ #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ FTIM1_GPCM_TRAD(0x1f)) #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ - FTIM2_GPCM_TCH(0x0) | \ + FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0x1f)) #define CONFIG_SYS_CS2_FTIM3 0x0 @@ -332,9 +328,9 @@ #define CONFIG_SYS_INIT_RAM_LOCK #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 -#define CONFIG_SYS_INIT_RAM_END 0x00004000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET @@ -380,7 +376,6 @@ /* Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) @@ -389,7 +384,6 @@ #define CONFIG_NS16550_MIN_FUNCTIONS #endif -#define CONFIG_SERIAL_MULTI /* Enable both serial ports */ #define CONFIG_SYS_CONSOLE_IS_IN_ENV #define CONFIG_SYS_BAUDRATE_TABLE \ @@ -398,20 +392,6 @@ #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) -/* Use the HUSH parser */ -#define CONFIG_SYS_HUSH_PARSER - -/* - * Pass open firmware flat tree - */ -#define CONFIG_OF_LIBFDT -#define CONFIG_OF_BOARD_SETUP -#define CONFIG_OF_STDOUT_VIA_ALIAS - -/* new uImage format support */ -#define CONFIG_FIT -#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ - #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_FSL #define CONFIG_SYS_FSL_I2C_SPEED 400000 @@ -424,24 +404,15 @@ /* I2C EEPROM */ /* enable read and write access to EEPROM */ #define CONFIG_CMD_EEPROM -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 -#define CONFIG_CMD_I2C - /* eSPI - Enhanced SPI */ -#define CONFIG_FSL_ESPI -#define CONFIG_SPI_FLASH -#define CONFIG_SPI_FLASH_SPANSION -#define CONFIG_SPI_FLASH_EON -#define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #ifdef CONFIG_TSEC_ENET -#define CONFIG_NET_MULTI #define CONFIG_MII /* MII PHY management */ #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ #define CONFIG_TSEC1 1 @@ -498,16 +469,16 @@ /* * Command line configuration. */ -#include - #define CONFIG_CMD_ERRATA -#define CONFIG_CMD_ELF #define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_SETEXPR #define CONFIG_CMD_REGINFO +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#endif + /* * Miscellaneous configurable options */ @@ -546,7 +517,6 @@ /* default location for tftp and bootm */ #define CONFIG_LOADADDR 1000000 -#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ #define CONFIG_BAUDRATE 115200 @@ -574,4 +544,6 @@ #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND +#include + #endif /* __CONFIG_H */