X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2FC29XPCIE.h;h=e24b9233687eef4dcccd8c3c8a842e95b25d22b2;hb=cf1331f85397d0612eec028061aeb308f505ab24;hp=69ca0a13e4afa280029f6e6c90c05c81ba85599e;hpb=e222b1f36fedb0363dbc21e0add7dc3848bae553;p=u-boot diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index 69ca0a13e4..e24b923368 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -12,6 +12,8 @@ #define __CONFIG_H #define CONFIG_PHYS_64BIT +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #ifdef CONFIG_C29XPCIE #define CONFIG_PPC_C29X @@ -24,8 +26,6 @@ #endif #ifdef CONFIG_NAND -#define CONFIG_SPL -#define CONFIG_TPL #ifdef CONFIG_TPL_BUILD #define CONFIG_SPL_NAND_BOOT #define CONFIG_SPL_FLUSH_IMAGE @@ -87,8 +87,8 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE /* BOOKE */ #define CONFIG_E500 /* BOOKE e500 family */ -#define CONFIG_MPC85xx #define CONFIG_FSL_IFC /* Enable IFC Support */ +#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ #define CONFIG_PCI /* Enable PCI/PCIE */ @@ -320,7 +320,7 @@ #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ FTIM1_GPCM_TRAD(0x1f)) #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ - FTIM2_GPCM_TCH(0x0) | \ + FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0x1f)) #define CONFIG_SYS_CS2_FTIM3 0x0 @@ -339,7 +339,7 @@ - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) #define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) /* @@ -509,6 +509,12 @@ #define CONFIG_CMD_SETEXPR #define CONFIG_CMD_REGINFO +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#endif + /* * Miscellaneous configurable options */ @@ -575,4 +581,6 @@ #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND +#include + #endif /* __CONFIG_H */