X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2FCANBT.h;h=7029dbddef2c48aa294d3cbdf0cbeadcad63db08;hb=258c37b147353bc522ffc33dfbd7d0d9cd7c32d7;hp=8e09c52764699d9f59b0bb56d3080059656fb27b;hpb=49cf7e8ee7ef943fdfe866ce28410b0bfbf6a26c;p=u-boot

diff --git a/include/configs/CANBT.h b/include/configs/CANBT.h
index 8e09c52764..7029dbddef 100644
--- a/include/configs/CANBT.h
+++ b/include/configs/CANBT.h
@@ -57,13 +57,22 @@
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
 
 
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
 /*
  * Command line configuration.
  */
 #include <config_cmd_default.h>
 
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_EEPROM	   
+#define CONFIG_CMD_EEPROM
 
 #undef CONFIG_CMD_NET
 
@@ -172,15 +181,6 @@
 /* mask of address bits that overflow into the "EEPROM chip address"	*/
 #define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
 
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		8192	/* For AMCC 405 CPUs			*/
-#define CFG_CACHELINE_SIZE	32	/* ...			*/
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
 /*
  * Init Memory Controller:
  *